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DP5Z2MX16PAJ3-90B

Description
Flash Module, 2MX16, 90ns, CQCC48, HERMETIC SEALED, J-LEAD, CERAMIC, SLCC-48
Categorystorage    storage   
File Size641KB,25 Pages
ManufacturerB&B Electronics Manufacturing Company
Download Datasheet Parametric View All

DP5Z2MX16PAJ3-90B Overview

Flash Module, 2MX16, 90ns, CQCC48, HERMETIC SEALED, J-LEAD, CERAMIC, SLCC-48

DP5Z2MX16PAJ3-90B Parametric

Parameter NameAttribute value
Parts packaging codeLCC
package instructionHERMETIC SEALED, J-LEAD, CERAMIC, SLCC-48
Contacts48
Reach Compliance Codeunknown
ECCN code3A001.A.2.C
Maximum access time90 ns
JESD-30 codeR-CQCC-J48
memory density33554432 bit
Memory IC TypeFLASH MODULE
memory width16
Number of functions1
Number of terminals48
word count2097152 words
character code2000000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize2MX16
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeQCCJ
Package shapeRECTANGULAR
Package formCHIP CARRIER
Parallel/SerialPARALLEL
Programming voltage5 V
Certification statusNot Qualified
Maximum seat height5.842 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
typeNOR TYPE
Base Number Matches1
32 Megabit FLASH EEPROM
PRELIMINARY
DESCRIPTION:
The DP5Z2MX16PAn3 “SLCC” devices are a revolutionary new memory
subsystem using Dense-Pac Microsystems’ ceramic Stackable Leadless Chip
Carriers (SLCC). Available unleaded, straight leaded, “J” leaded, gullwing
leaded packages, or mounted on a 50-pin PGA co-fired ceramic substrate.
The Device packs 32-Megabits of FLASH EEPROM in an area as small as
0.463 in2 while maintaining a total height as low as 0.171 inches.
The DP5Z2MX16PAn3 is a 2 Meg x 8 FLASH EEPROM based memory
module. Each SLCC is hermetically sealed making the module suitable for
commercial, industrial and military applications.
By using SLCCs, the “Stack” family of modules offer a higher board density
of memory than available with conventional through-hole, surface mount or
hybrid techniques.
DP5Z2MX16PAn3
DP5Z2MX16PAY3
DP5Z2MX16PAI3
FEATURES:
Organization: 2 Meg x 16
Fast Access Times: 70*, 90, 120, 150ns (max.)
* V
DD
= 5.0V
±
5%
Single 5.0 Volt Power Supply
High-Density Symmetrically Blocked Architecture
- 32 Uniform Sectors of 64 Kbyts Each
Extended Cycling Capability
- 100,000 Write/Erase Cycles per Sector
Automated Erase and Program Cycles
- Command User Interface
- Status Register
SRAM-Compatible Write Interface
Hardware Data Protection Feature
Packages Available:
DP5Z2MX16PAY3
DP5Z2MX16PAI3
DP5Z2MX16PAH3
DP5Z2MX16PAJ3
DP5Z2MX16PAA3
DP5Z2MX16PAJ3
- Erase / Write Lockout during Power Transitions
48 - Pin SLCC
48 - Pin Straight Leaded SLCC
48 - Pin Gullwing Leaded SLCC
48 - Pin J Leaded SLCC
50 - Pin PGA Dense-SLCC
DP5Z2MX16PAA3
DP5Z2MX16PAH3
30A161-A2
Rev. A
This document contains information on a product under consideration for
development at Dense-Pac Microsystems, Inc. Dense-Pac reserves the right
to
change
or discontinue information on this product without prior notice.
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