PCA9518A
Expandable 5-channel I
2
C-bus hub
Rev. 03 — 3 December 2008
Product data sheet
1. General description
The PCA9518A is a CMOS integrated circuit intended for application in I
2
C-bus and
SMBus systems.
While retaining all the operating modes and features of the I
2
C-bus system, it permits
extension of the I
2
C-bus by buffering both the data (SDA) and the clock (SCL) lines, thus
enabling virtually an unlimited number of buses of 400 pF.
The I
2
C-bus capacitance limit of 400 pF restricts the number of devices and bus length.
Using the PCA9518A enables the system designer to divide the bus into an unlimited
number of segments off of a hub where any segment to segment transition sees only one
repeater delay and is multiple master capable on each segment.
Using multiple PCA9518A parts, any width hub (in multiples of five)
1
can be implemented
using the expansion pins.
The PCA9518A is a wider voltage range (2.3 V to 3.6 V) version of the PCA9518 and also
improves partial power-down performance, keeping I
2
C-bus I/O pins in high-impedance
state when V
DD
is below 2.0 V.
A PCA9518 cluster cannot be put in series with a PCA9515/16 or with another
PCA9518 cluster.
Multiple PCA9518 devices can be grouped with other PCA9518
devices into any size cluster thanks to the EXPxxxn pins that allow the I
2
C-bus signals to
be sent/received from/to one PCA9518 to/from another PCA9518 within the cluster. Since
there is no direction pin, slightly different ‘legal’ low voltage levels are used to avoid
lock-up conditions between the input and the output of individual repeaters in the cluster.
A ‘regular LOW’ applied at the input of any of the PCA9518 devices will then be
propagated as a ‘buffered LOW’ with a slightly higher LOW value to all enabled outputs in
the PCA9518 cluster. When this ‘buffered LOW’ is applied to a PCA9515 and PCA9516 or
separate PCA9518 cluster (not connected via the EXPxxxn pins) in series, the second
PCA9515 and PCA9516 or PCA9518 cluster will not recognize it as a ‘regular LOW’ and
will not propagate it as a ‘buffered LOW’ again. The PCA9510/9511/9513/9514 and
PCA9512 cannot be used in series with the PCA9515 and PCA9516 or PCA9518 either,
but can be used in series with themselves since they use shifting instead of static offsets
to avoid lock-up conditions. This note is applicable to the ‘A’ versions of these devices
also.
1.
Only four ports per device are available if individual Enable is required.
NXP Semiconductors
PCA9518A
Expandable 5-channel I
2
C-bus hub
2. Features
I
I
I
I
I
I
I
I
I
I
I
I
Expandable 5 channel, bidirectional buffer
I
2
C-bus and SMBus compatible
Active HIGH individual repeater enable inputs
Open-drain input/outputs
Lock-up free operation
Supports arbitration and clock stretching across the repeater
Accommodates Standard-mode and Fast-mode I
2
C-bus devices and multiple masters
Powered-off high-impedance I
2
C-bus pins
Operating supply voltage range of 2.3 V to 3.6 V
5 V tolerant I
2
C-bus and enable pins
0 Hz to 400 kHz clock frequency
2
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
I
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
I
Package offerings: SO20 and TSSOP20
3. Ordering information
Table 1.
Ordering information
T
amb
=
−
40
°
C to +85
°
C
Type number
PCA9518AD
PCA9518APW
Topside mark Package
Name
PCA9518AD
PA9518A
SO20
TSSOP20
Description
plastic small outline package; 20 leads; body width 7.5 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
Version
SOT163-1
SOT360-1
2.
The maximum system operating frequency may be less than 400 kHz because of the delays added by the repeater.
© NXP B.V. 2008. All rights reserved.
PCA9518A_3
Product data sheet
Rev. 03 — 3 December 2008
2 of 23
NXP Semiconductors
PCA9518A
Expandable 5-channel I
2
C-bus hub
4. Block diagram
V
DD
EXPSCL1
EXPSCL2
BUFFER
BUFFER
SCL1
BUFFER
HUB
LOGIC
BUFFER
SCL2
BUFFER
PCA9518A
SCL0
SCL4
SCL3
EXPSDA1
EXPSDA2
BUFFER
BUFFER
SDA1
BUFFER
HUB
LOGIC
BUFFER
SDA2
BUFFER
SDA3
SDA4
SDA0
EN1
EN2
002aac530
EN4
EN3
V
SS
Fig 1.
Block diagram of PCA9518A
A more detailed view of
Figure 1
buffer is shown in
Figure 2.
data
to output
in
inc
enable
002aac531
Fig 2.
Buffer detail
The output pull-down voltage of each internal buffer is set for approximately 0.5 V, while
the input threshold of each internal buffer is set about 0.07 V lower, when the output is
internally driven LOW. This prevents a lock-up condition from occurring.
PCA9518A_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 3 December 2008
3 of 23
NXP Semiconductors
PCA9518A
Expandable 5-channel I
2
C-bus hub
5. Pinning information
5.1 Pinning
EXPSCL1
EXPSCL2
SCL0
SDA0
SCL1
SDA1
EN1
SCL2
SDA2
1
2
3
4
5
6
7
8
9
20 V
DD
19 EXPSDA2
18 EXPSDA1
17 EN4
16 SDA4
15 SCL4
14 EN3
13 SDA3
12 SCL3
11 EN2
002aac528
EXPSCL1
EXPSCL2
SCL0
SDA0
SCL1
SDA1
EN1
SCL2
SDA2
1
2
3
4
5
6
7
8
9
20 V
DD
19 EXPSDA2
18 EXPSDA1
17 EN4
16 SDA4
15 SCL4
14 EN3
13 SDA3
12 SCL3
11 EN2
002aac529
PCA9518AD
PCA9518APW
V
SS
10
V
SS
10
Fig 3.
Pin configuration for SO20
Fig 4.
Pin configuration for TSSOP20
5.2 Pin description
Table 2.
Symbol
EXPSCL1
EXPSCL2
SCL0
SDA0
SCL1
SDA1
EN1
SCL2
SDA2
V
SS
EN2
SCL3
SDA3
EN3
SCL4
SDA4
EN4
EXPSDA1
EXPSDA2
V
DD
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Description
expandable serial clock pin 1
expandable serial clock pin 2
serial clock bus 0
serial data bus 0
serial clock bus 1
serial data bus 1
active HIGH bus 1 enable input
serial clock bus 2
serial data bus 2
supply ground
active HIGH bus 2 enable input
serial clock bus 3
serial data bus 3
active HIGH bus 3 enable input
serial clock bus 4
serial data bus 4
active HIGH bus 4 enable input
expandable serial data pin 1
expandable serial data pin 2
supply voltage
PCA9518A_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 3 December 2008
4 of 23
NXP Semiconductors
PCA9518A
Expandable 5-channel I
2
C-bus hub
6. Functional description
The PCA9518A CMOS integrated circuit is a five-way hub repeater, which enables
I
2
C-bus and similar bus systems to be expanded in increments of five with only one
repeater delay and no functional degradation of system performance.
The PCA9518A CMOS integrated circuit contains five multi-directional, open-drain buffers
specifically designed to support the standard low-level contention arbitration of the
I
2
C-bus. Except during arbitration or clock stretching, the PCA9518A acts like a pair of
non-inverting, open-drain buffers, one for SDA and one for SCL.
Refer to
Figure 1 “Block diagram of PCA9518A”.
6.1 Enable
The enable pins EN1 through EN4 are active HIGH and have internal pull-up resistors.
Each enable pin ENn controls its associated SDAn and SCLn ports. When LOW, the ENn
pin blocks the inputs from SDAn and SCLn, as well as disabling the output drivers on the
SDAn and SCLn pins. The enable pins should only change state when both the global bus
and the local port are in an idle state to prevent system failures.
The active HIGH enable pins allow the use of open-drain drivers which can be wire-ORed
to create a distributed enable where either centralized control signal (master) or spoke
signal (sub-master) can enable the channel when it is idle.
Unused channels must have pull-up resistors unless their enable pin (ENn) is
always
LOW. Port 0 must always have pull-up resistors since it is always present in the bus and
cannot be disabled.
6.2 Expansion
The PCA9518A includes 4 open-drain I/O pins used for expansion. Two expansion pins,
EXPSDA1 and EXPSDA2 are used to communicate the internal state of the serial data
within each hub to the other hubs. The EXPSDA1 pins of all hubs are connected together
to form an open-drain bus. Similarly, all EXPSDA2 pins, EXPSCL1 pins, and all EXPSCL2
pins are connected together forming a 4-wire bus between hubs.
When it is necessary to be able to deselect every port, each expansion device only
contributes 4 ports which can be enabled or disables because the fifth does not have an
enable pin.
Pull-up resistors are required on the EXPxxxn
3
pins even if only one PCA9518A is used.
6.3 I
2
C-bus systems
As with the standard I
2
C-bus system, pull-up resistors are required to provide the logic
HIGH levels on the buffered bus. (Standard open-collector or open-drain configuration of
the I
2
C-bus). The size of these pull-up resistors depends on the system, but each side of
the repeater must have a pull-up resistor. This part is designed to work with
Standard-mode (0 Hz to 100 kHz) and Fast-mode (0 Hz to 400 kHz) I
2
C-bus devices in
addition to SMBus devices. Standard-mode I
2
C-bus devices only specify 3 mA output
drive; this limits the termination current to 3 mA in a generic I
2
C-bus system where
3.
‘xxxn’ is SDA1, SDA2, SCL1 or SCL2. ‘xxx’ is SDA or SCL.
© NXP B.V. 2008. All rights reserved.
PCA9518A_3
Product data sheet
Rev. 03 — 3 December 2008
5 of 23
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