PCA9541BS/01 datasheet, PDF - EEWORLD Datasheet

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PCA9541BS/01: Description2-to-1 I2C-bus master selector with interrupt logic and reset; File Size184KB，43 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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PCA9541BS/01 Overview

2-to-1 I2C-bus master selector with interrupt logic and reset

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PCA9541

2-to-1 I

C-bus master selector with interrupt logic and reset

Rev. 06 — 11 September 2008

Product data sheet

1. General description

The PCA9541 is a 2-to-1 I

C-bus master selector designed for high reliability dual master

C-bus applications where system operation is required, even when one master fails or

the controller card is removed for maintenance. The two masters (for example, primary

and back-up) are located on separate I

C-buses that connect to the same downstream

C-bus slave devices. I

C-bus commands are sent by either I

C-bus master and are used

to select one master at a time. Either master at any time can gain control of the slave

devices if the other master is disabled or removed from the system. The failed master is

isolated from the system and will not affect communication between the on-line master

and the slave devices on the downstream I

C-bus.

Three versions are offered for different architectures. PCA9541/01 with channel 0

selected at start-up, PCA9541/02 with channel 0 selected after start-up and after STOP

condition is detected, and PCA9541/03 with no channel selected after start-up.

The interrupt outputs are used to provide an indication of which master has control of the

bus. One interrupt input (INT_IN) collects downstream information and propagates it to

the 2 upstream I

C-buses (INT0 and INT1) if enabled. INT0 and INT1 are also used to let

the previous bus master know that it is not in control of the bus anymore and to indicate

the completion of the bus recovery/initialization sequence. Those interrupts can be

disabled and will not generate an interrupt if the masking option is set.

A bus recovery/initialization if enabled sends nine clock pulses, a not acknowledge, and a

STOP condition in order to set the downstream I

C-bus devices to an initialized state

before actually switching the channel to the selected master.

An interrupt is sent to the upstream channel when the recovery/initialization procedure is

completed.

An internal bus sensor senses the downstream I

C-bus trafﬁc and generates an interrupt

if a channel switch occurs during a non-idle bus condition. This function is enabled when

the PCA9541 recovery/initialization is not used. The interrupt signal informs the master

that an external I

C-bus recovery/initialization needs to be performed. It can be disabled

and an interrupt will not be generated.

The pass gates of the switches are constructed such that the V

pin can be used to limit

the maximum high voltage, which will be passed by the PCA9541. This allows the use of

different bus voltages on each pair, so that 1.8 V, 2.5 V, or 3.3 V devices can communicate

with 5 V devices without any additional protection.

The PCA9541 does not isolate the capacitive loading on either side of the device, so the

designer must take into account all trace and device capacitances on both sides of the

device, and pull-up resistors must be used on all channels.

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