PX1011B
PCI Express stand-alone X1 PHY
Rev. 03 — 20 October 2008
Product data sheet
1. General description
The PX1011B is a high-performance, low-power, single-lane PCI Express electrical
PHYsical layer (PHY) that handles the low level PCI Express protocol and signaling. The
PX1011B PCI Express PHY is compliant to the
PCI Express Base Specification,
Rev. 1.0a,
and
Rev. 1.1.
The PX1011B includes features such as Clock and Data
Recovery (CDR), data serialization and de-serialization, 8b/10b encoding, analog buffers,
elastic buffer and receiver detection, and provides superior performance to the Media
Access Control (MAC) layer devices.
The PX1011B is a 2.5 Gbit/s PCI Express PHY with 8-bit data PXPIPE interface. Its
PXPIPE interface is a superset of the PHY Interface for the PCI Express (PIPE)
specification, enhanced and adapted for off-chip applications with the introduction of a
source synchronous clock for transmit and receive data. The 8-bit data interface operates
at 250 MHz with SSTL_2 signaling. The SSTL_2 signaling is compatible with the I/O
interfaces available in FPGA products.
The PX1011B PCI Express PHY supports advanced power management functions. The
PX1011BI is for the industrial temperature range (−40
°C
to +85
°C).
2. Features
2.1 PCI Express interface
I
I
I
I
I
I
I
I
I
I
Compliant to
PCI Express Base Specification 1.1
Single PCI Express 2.5 Gbit/s lane
Data and clock recovery from serial stream
Serializer and De-serializer (SerDes)
Receiver detection
8b/10b coding and decoding, elastic buffer and word alignment
Supports loopback
Supports direct disparity control for use in transmitting compliance pattern
Supports lane polarity inversion
Low jitter and Bit Error Rate (BER)
2.2 PHY/MAC interface
I
I
I
I
Based on Intel PHY Interface for PCI Express architecture v1.0 (PIPE)
Adapted for off-chip with additional synchronous clock signals (PXPIPE)
8-bit parallel data interface for transmit and receive at 250 MHz
2.5 V SSTL_2 class I signaling
NXP Semiconductors
PX1011B
PCI Express stand-alone X1 PHY
2.3 JTAG interface
I
JTAG (IEEE 1149.1) boundary scan interface
I
Built-In Self Test (BIST) controller tests SerDes and I/O blocks at speed
I
3.3 V CMOS signaling
2.4 Power management
I
Dissipates < 300 mW in L0 normal mode
I
Support power management of L0, L0s and L1
2.5 Clock
I
100 MHz external reference clock with
±300
ppm tolerance
I
Supports spread spectrum clock to reduce EMI
I
On-chip reference clock termination
2.6 Miscellaneous
I
LFBGA81 leaded or lead-free packages
I
Operating ambient temperature
N
Commercial: 0
°C
to +70
°C
N
Industrial:
−40 °C
to +85
°C
I
ESD protection voltage for Human Body Model (HBM): 2000 V
3. Quick reference data
Table 1.
V
DDD1
V
DDD2
V
DDD3
V
DD
V
DDA1
V
DDA2
f
clk(ref)
T
amb
Quick reference data
Conditions
for JTAG I/O
for SSTL_2 I/O
for core
for high-speed
serial I/O and PVT
for serializer
for serializer
operating
commercial
industrial
0
−40
-
-
+70
+85
°C
°C
Min
3.0
2.3
1.15
1.15
1.15
3.0
99.97
Typ
3.3
2.5
1.2
1.2
1.2
3.3
100
Max
3.6
2.7
1.3
1.3
1.3
3.6
100.03
Unit
V
V
V
V
V
V
MHz
digital supply voltage 1
digital supply voltage 2
digital supply voltage 3
supply voltage
analog supply voltage 1
analog supply voltage 2
reference clock frequency
ambient temperature
Symbol Parameter
PX1011B_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 20 October 2008
2 of 30
NXP Semiconductors
PX1011B
PCI Express stand-alone X1 PHY
4. Ordering information
Table 2.
Ordering information
Solder process
Pb-free (SnAgCu
solder ball compound)
SnPb solder ball
compound
Package
Name
PX1011B-EL1/G
PX1011B-EL1/N
LFBGA81
LFBGA81
LFBGA81
Description
plastic low profile fine-pitch ball grid array package;
81 balls; body 9
×
9
×
1.05 mm
plastic low profile fine-pitch ball grid array package;
81 balls; body 9
×
9
×
1.05 mm
plastic low profile fine-pitch ball grid array package;
81 balls; body 9
×
9
×
1.05 mm
Version
SOT643-1
SOT643-1
SOT643-1
Type number
PX1011BI-EL1/G Pb-free (SnAgCu
solder ball compound)
5. Marking
Table 3.
Line
A
B
C
Leaded package marking
Marking
PX1011B-EL1/N
xxxxxxx
2PNyyww
Description
full basic type number
diffusion lot number
manufacturing code:
2 = diffusion site
P = assembly site
N = leaded
yy = year code
ww = week code
Table 4.
Line
A
B
C
Lead-free package marking
Marking
PX1011B-EL1/G
PX1011BI-EL1/G
[1]
xxxxxxx
2PGyyww
diffusion lot number
manufacturing code:
2 = diffusion site
P = assembly site
G = lead-free
yy = year code
ww = week code
[1]
Industrial temperature range.
Description
full basic type number
PX1011B_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 20 October 2008
3 of 30
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