NAND16GW3F4A
16-Gbit (2 x 8 Gbits), two Chip Enable, 4224-byte page,
3 V supply, multiplane architecture, SLC NAND flash memories
Preliminary Data
Features
■
High-density SLC NAND flash memory
– 16 Gbits of memory array
– Cost-effective solutions for mass storage
applications
NAND interface
– x8 bus width
– Multiplexed address/data
Supply voltage: V
DD
= 2.7 to 3.6 V
Page size: (4096 + 128 spare) bytes
Block size: (256K + 8K spare) bytes
Multiplane architecture
– Array split into two independent planes
– All operations can be performed on both
planes simultaneously
Page read/program
– Random access: 25 µs (max)
– Sequential access: 25 ns (min)
– Page program operation time: 500 µs (typ)
Multiplane page program time (2 pages):
500 µs (typ)
Copy-back program
– Automatic block download without latency
time
Fast block erase
– Block erase time: 1.5 ms (typ)
– Multiplane block erase time (2 blocks):
1.5 ms (typ)
Status register
Electronic signature
Chip enable ‘don’t care’
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TSOP48 12 x 20 mm (N)
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Data protection
– Hardware program/erase locked during
power transitions
Security features
– OTP area
– Serial number (unique ID)
Development tools
– Error correction code models
– Bad block management and wear leveling
algorithm
– HW simulation models
Data integrity
– 100,000 program/erase cycles (with ECC)
– 10 years data retention
RoHS compliant packages
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November 2009
Rev 3
1/17
www.numonyx.com
1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
NAND16GW3F4A
Contents
1
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1
2.2
Bad blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Parallel operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
Inputs/outputs (I/O0-I/O7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Address Latch Enable (AL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Command Latch Enable (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chip Enable (E
1
, E
2
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Read Enable (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Ready/Busy (RB
1
, RB
2
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
V
DD
supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
V
SS
ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4
5
6
7
8
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2/17
NAND16GW3F4A
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Valid blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package mechanical data. . . . . 14
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3/17
NAND16GW3F4A
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
TSOP48 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline . . . . . . . . . . . . 14
4/17
NAND16GW3F4A
Description
1
Description
The NAND16GW3F4A is part of the single level cell (SLC), 4224-byte page family of non-
volatile NAND flash memories. The device has a density of 16 Gbits and combines two 8-
Gbit dice in a stacked device. Each dice has its own Chip Enable and Ready/Busy pin. This
means that each 8-Gbit dice can be driven independently using the relative Chip Enable pin.
The device operates from a 3 V power supply.
In addition, each 8-Gbit dice has its own maximum number of bad blocks and its own
electronic signature code.
This document must be read in conjunction with the NANDxxGW3F2A datasheet, which
fully details all the specifications required to operate the 8-Gbit flash memory device.
The device is available in TSOP48 (12 × 20 mm) package and is shipped from the factory
with block 0 always valid and the memory content bits, in valid blocks, erased to ‘1’.
Refer to
Table 8: Ordering information scheme
for information on how to order this device.
Table 1.
Device summary
Timings
Operating
Random
Page
Sequential
Block size Memory array voltage
access
program
access
(V
DD
)
time
(typ)
time (min)
(max)
Bus
Density
width
Page size
Block
erase
(typ)
Package
16
Gbits
x8
4096+
128 bytes
256K +
8K bytes
64 pages x
8192 blocks
2.7 to
3.6 V
25 µs
25 ns
500 µs
1.5 ms TSOP48
5/17
Recruitment
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