3.3 VOLT TIME SLOT INTERCHANGE
DIGITAL SWITCH WITH RATE
MATCHING 32,768
X
32,768 CHANNELS
IDT72V73273
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Up to 64 serial input and output streams
Maximum 32,768 x 32,768 channel non-blocking switching
Accepts data streams at 2.048Mb/s, 4.096Mb/s, 8.192Mb/s,
16.384Mb/s or 32.768Mb/s
Rate matching capability: rate selectable on both RX and TX
in eight groups of 8 streams
Optional Output Enable Indication Pins for external driver
High-Z control
Per-channel Variable Delay Mode for low-latency applications
Per-channel Constant Delay Mode for frame integrity applications
Enhanced Block programming capabilities
TX/RX Internal Bypass
Automatic identification of ST-BUS
and GCI serial streams
Per-stream frame delay offset programming
Per-channel High-Impedance output control
Per-channel processor mode to allow microprocessor writes to TX
streams
Bit Error Rate Testing (BERT) for testing
Direct microprocessor access to all internal memories
Selectable Synchronous and Asynchronous microprocessor
bus timing modes
IEEE-1149.1 (JTAG) Test Port
Available in 208-pin (28mm x 28mm) Plastic Quad Flatpack (PQFP)
and 208-pin (17mm x 17mm) Plastic Ball Grid Array (PBGA)
Operating Temperature Range -40°C to +85°C
°
°
DESCRIPTION:
The IDT72V73273 has a non-blocking switch capacity of 32,768 x 32,768
channels at 32.768Mb/s. With 64 inputs and 64 outputs, programmable per
stream control, and a variety of operating modes the IDT72V73273 is
designed for the TDM time slot interchange function in either voice or data
applications.
Some of the main features of the IDT72V73273 are LOW power 3.3 Volt
operation, automatic ST-BUS
®
/GCI sensing, memory block programming,
simple microprocessor interface , JTAG Test Access Port (TAP) and per
stream programmable input offset delay, variable or constant throughput
modes, output enable and processor mode, BER testing, bypass mode, and
advanced block programming.
FUNCTIONAL BLOCK DIAGRAM
V
CC
GND
RESET
ODE
RX0-7
RX8-15
RX16-23
RX24-31
RX32-39
RX40-47
RX48-55
RX56-63
TX0-TX7
Data Memory
MUX
TX8-15/OEI0-7
TX16-23
Receive
Serial Data
Streams
Internal
Registers
Connection
Memory
Transmit
Serial Data
Streams
TX24-31/OEI16-23
TX32-39
TX40-47/OEI32-39
TX48-55
TX56-63/OEI48-55
Timing Unit
Microprocessor Interface
JTAG Port
C32i
F32i
S/A
DS CS
R/W A0-A15
BEL DTA/
D0-D15
BEH
TMS TDI TCK TDO
TRST
6140 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The ST-BUS
is a trademark of Mitel Corp.
OCTOBER 2003
DSC-6140/3
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice
IDT72V73273 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH WITH RATE MATCHING 32,768 x 32,768 CHANNELS
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION
SYMBOL
NAME
I/O
PQFP
PIN NO.
A0-A15
BEL
C32i
CS
D0-15
DS
DTA/BEH
Address 0-15
Byte Enable LOW
Clock
Chip Select
Data Bus 0-15
Data Strobe
Data Transfer
Acknowledgment
Active LOW Output
/Byte Enable HIGH
I
I
I
I
I/O
I
I/O
*See PQFP
Table Below
31
2
12
*See PQFP
Table Below
11
32
PBGA
PIN NO.
*See PBGA
Table Below
L4
A1
E1
*See PBGA
Table Below
D4
K2
These address lines access all internal memories.
In synchronous mode, this input will enable the lower byte (D0-7) on to the data
bus.
Serial clock for shifting data in/out on the serial data streams. This input accepts
a 32.768MHz clock.
Active LOW input used by a microprocessor to activate the microprocessor port
of the device.
These pins are the data bus of the microprocessor port.
This active LOW input works in conjunction with
CS
to enable the read and write
operations. This active LOW input sets the data bus lines (D0-D15).
In asynchronous mode this pin indicates that a data bus transfer is complete.
When the bus cycle ends, this pin drives HIGH and then High-Z allowing for
faster bus cycles with a weaker pull-up resistor. A pull-up resistor is required to
hold a HIGH level when the pin is High-Z. When the device is in
synchronous bus mode, this pin acts as an input and will enable the upper byte
(D8-15) on to the data bus.
This input accepts and automatically identifies frame synchronization signals
formatted according to ST-BUS
and GCI specifications.
Ground.
This is the output enable control for the TX serial outputs. When ODE input is
LOW and the OSB bit of the CR register is LOW, all TX outputs are in a High-
Impedance state. If this input is HIGH, the TX output drivers are enabled.
However, each channel may still be put into a High-Impedance state by using
the per channel control bits in the Connection Memory HIGH.
Serial data Input Stream. These streams may have data rates of 2.048Mb/s,
4.096Mb/s, 8.192Mb/s, 16.384Mb/s, or 32.768Mb/s depending upon the
selection in Receive Data Rate Selection Register (RDRSR).
This input (active LOW) puts the device in its reset state that clears the device
internal counters, registers and brings TX0-63 and microport data outputs to a
High-Impedance state. The
RESET
pin must be held LOW for a minimum of
20ns to reset the device.
This input controls the direction of the data bus lines (D0-D15) during a
microprocessor access.
This input will select between asynchronous microprocessor bus timing and
synchronous microprocessor bus timing. In synchronous mode,
DTA/BEH
acts as the
BEH
input and is used in conjunction with
BEL
to output data on the
data bus. In asynchronous bus mode,
BEL
is tied LOW and
DTA/BEH
acts as
the DTA, data bus acknowledgment output.
Provides the clock to the JTAG test logic.
JTAG serial test instructions and data are shifted in on this pin. This pin is pulled
HIGH by an internal pull-up when not driven.
JTAG serial data is output on this pin on the falling edge of TCK. This pin is held i
in High-Impedance state when JTAG scan is not enabled.
JTAG signal that controls the state transitions of the TAP controller. This pin is
pulled HIGH by an internal pull-up when not driven.
Asynchronously initializes the JTAG TAP controller by putting it in the Test-
Logic-Reset state. This pin is pulled by an internal pull-up when not driven. This
pin should be pulsed LOW on power-up, or held LOW, to ensure that the device
DESCRIPTION
F32i
GND
ODE
Frame Pulse
I
3
*See PQFP
Table Below
B1
*See PBGA
Table Below
A3
Output Drive Enable
I
207
RX0-63
RX Input 0 to 63
I
*See PQFP
Table Below
208
*See PBGA
Table Below
A2
RESET
Device Reset:
I
R/W
S/A
Read/Write
Synchronous/
Asynchronous
Bus Mode
I
I
13
5
E2
C1
TCK
TDI
TDO
TMS
TRST
Test Clock
Test Serial Data In
Test Serial Data Out
Test Mode Select
Test Reset
I
I
O
I
I
9
7
8
6
10
D2
C3
D1
C2
D3
4
IDT72V73273 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH WITH RATE MATCHING 32,768 x 32,768 CHANNELS
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION (CONTINUED)
SYMBOL
TX0-7
TX16-23
TX32-39
TX48-55
NAME
TX Output
I/O
O
PQFP
PIN NO.
*See PQFP
Table Below
PBGA
PIN NO.
*See PBGA Serial Data Output Stream. These streams may have data rates of 2.048Mb/s,
Table Below 4.096Mb/s, 8.192Mb/s,16.384Mb/s, or 32.768Mb/s depending upon the
selection in Transmit Data Rate Selection Register (TDRSR).
*See PBGA When output streams are selected via TDRSR, these pins are the TX output
Table Below streams. When output enable indication function is selected, these pins reflect the
active or High-Impedance status for the corresponding TX output stream.
*See PBGA +3.3 Volt Power Supply.is in the normal functional mode.
Table Below
DESCRIPTION
TX8-15/OEI0-7
TX Output /Output Enable
TX24-31/OEI16-23 Indication
TX40-47/OEI32-39
TX56-63/OEI48-55
V
CC
O
*See PQFP
Table Below
*See PQFP
Table Below
PQFP PIN NUMBER TABLE
SYMBOL
NAME
I/O
DESCRIPTION
A0-A15
D0-D15
GND
RX0-63
Address A0-A15
Data Bus 0-15
Ground
RX Input 0 to 63
I
I/O
I
15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30.
54, 53, 52, 51, 48, 47, 46, 45, 42, 41, 40, 39, 36, 35, 34, 33.
1, 38, 44, 50, 68, 74, 80, 106, 112, 118, 143, 149, 155, 181, 187, 193.
206, 205 , 204 , 203 , 202 , 201 , 200 , 199 , 198 , 175 , 174 , 173 , 172 , 171 , 170 , 169 , 168 , 167 ,166 ,
165 , 164 , 163 , 162 , 161 , 138 , 137 , 136 , 135 , 134 , 133 , 132 , 131 , 130 ,129 , 128 , 127 , 126 , 125 ,
124 , 123 , 100 , 99, 98 , 97 , 96 , 95 , 94 , 93 , 92 , 91 , 90 , 89 , 88 , 87 , 86 , 85, 62 , 61 , 60 , 59, 58 ,
57 , 56 , 55 .
198, 197, 196, 195, 192, 191, 190, 189.
160, 159, 158, 157, 154, 153, 152, TX23=151.
122, 121, 120, 119, 116, 115, 114, 113.
84, 83, 82, 81, 78, 77, 76, 75.
186, 185, 184, 183, 180, 179,178, 177.
148, 147, 146, 145, 142, 141, 140, 139.
110, 109, 108, 107, 104, 103, 102, 101.
72, 71, 70, 69, 66, 65, 64, 63.
4, 14, 37, 43, 49, 67, 73, 79, 105, 111, 117, 144, 150, 156, 182, 188, 194.
TX0-7
TX16-23
TX32-39
TX48-55
TX8-15/OEI0-7
TX24-31/OEI16-23
TX40-47/OEI32-39
TX56-63/OEI48-55
Vcc
TX Output
O
TX Output/Output
O
PBGA PIN NUMBER TABLE
SYMBOL
NAME
I/O
DESCRIPTION
A0-A15
D0-D15
GND
RX0-63
Address A0-A15
Data Bus 0-15
Ground
RX Input 0 to 63
I
I/O
I
E3, E4, F1, F2, F3, F4, G1, G2, G3, H1, H2, H3, J3, J2, J1, K3.
T2, T1, R1, P1, P2, N1, N2, N3, M1, M2, M3, M4, L1, L2, L3, K1.
G7, G8, G9, G10, H7, H8, H9, H10, J7, J8, J9, J10, K7, K8, K9, K10.
B3, A4 , B4 , C4 , A5 , B5 , C5 , D5 , D11 , C11 , B11 , A11 , D12 , C12 , B12 , A12 , E13 , D13 , C13 ,
B13 , A13 , D14 , C14 , B14 , G16 , G15, G14 , H16 , H15 , H14 , J14 , J15 , J16 , K14 , K15 , K16 , L13,
L14 , L15 , L16 , R14 , T13, R13 , P13 , T12 , R12 , P12 , N12 , T11 , R11 , P11 , N11 , T10 , R10 , P10 ,
T9, N4 , P4 , R4 , T4, P3 , R3 , T3 , R2 .
A6, B6, ,C6 D6, A7, B7, C7, A8.
A14, B15, A15, A16, B16, C16, C15, D16.
M13, M14, M15, M16, N13, N14, N15, N16.
R9, P9, P8, R8, T8, P7, R7, T7.
B8, C8, C9, B9, A9, C10, B10, A10.
D15, E16, E15, E14, F16, F15, F14, F13.
P14, P15, P16, R16, T16, T15, R15, T14.
N6, P6, R6, T6, N5, P5, R5, T5.
B2, D7, D8, D9, D10, G4, G13, H4, H13, J4, J13, K4, K13, N7, N8, N9, N10.
5
TX0-7
TX16-23
TX32-39
TX48-55
TX8-15/OEI0-7
TX24-31/OEI16-23
TX40-47/OEI32-39
TX56-63/OEI48-55
Vcc
TX Output
O
TX Output/Output
O
Analog electronics
京公网安备 11010802033920号
EEWORLD
