Features
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Single 1.65V - 1.95V Supply
•
Serial Peripheral Interface (SPI) Compatible
•
•
– Supports SPI Modes 0 and 3
66 MHz Maximum Clock Frequency
Flexible, Uniform Erase Architecture
– 4-Kbyte Blocks
– 32-Kbyte Blocks
– 64-Kbyte Blocks
– Full Chip Erase
Individual Sector Protection with Global Protect/Unprotect Feature
– Sixteen 64-Kbyte Physical Sectors
Hardware Controlled Locking of Protected Sectors
Flexible Programming
– Byte/Page Program (1 to 256 Bytes)
Automatic Checking and Reporting of Erase/Program Failures
JEDEC Standard Manufacturer and Device ID Read Methodology
Low Power Dissipation
– 7 mA Active Read Current (Typical)
– 8 µA Deep Power-Down Current (Typical)
Endurance: 100,000 Program/Erase Cycles
Data Retention: 20 Years
Complies with Full Industrial Temperature Range
Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
– 8-lead SOIC (150-mil wide)
– 8-contact Ultra Thin DFN (5 mm x 6 mm x 0.6 mm)
– 11-ball dBGA (WLCSP)
•
•
•
•
•
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8-megabit
1.65-volt
Minimum
SPI Serial Flash
Memory
AT25DF081
•
•
•
•
1. Description
The AT25DF081 is a serial interface Flash memory device designed for use in a wide
variety of high-volume consumer based applications in which program code is shad-
owed from Flash memory into embedded or external RAM for execution. The flexible
erase architecture of the AT25DF081, with its erase granularity as small as 4-Kbytes,
makes it ideal for data storage as well, eliminating the need for additional data storage
EEPROM devices.
The physical sectoring and the erase block sizes of the AT25DF081 have been opti-
mized to meet the needs of today's code and data storage applications. By optimizing
the size of the physical sectors and erase blocks, the memory space can be used
much more efficiently. Because certain code modules and data storage segments
must reside by themselves in their own protected sectors, the wasted and unused
memory space that occurs with large sectored and large block erase Flash memory
devices can be greatly reduced. This increased memory space efficiency allows addi-
tional code routines and data storage segments to be added while still maintaining the
same overall device density.
3674E–DFLASH–8/08
The AT25DF081 also offers a sophisticated method for protecting individual sectors against
erroneous or malicious program and erase operations. By providing the ability to individually pro-
tect and unprotect sectors, a system can unprotect a specific sector to modify its contents while
keeping the remaining sectors of the memory array securely protected. This is useful in applica-
tions where program code is patched or updated on a subroutine or module basis, or in
applications where data storage segments need to be modified without running the risk of errant
modifications to the program code segments. In addition to individual sector protection capabili-
ties, the AT25DF081 incorporates Global Protect and Global Unprotect features that allow the
entire memory array to be either protected or unprotected all at once. This reduces overhead
during the manufacturing process since sectors do not have to be unprotected one-by-one prior
to initial programming.
Specifically designed for use in 1.8-volt systems, the AT25DF081 supports read, program, and
erase operations with a supply voltage range of 1.65V to 1.95V. No separate voltage is required
for programming and erasing.
2
AT25DF081
3674E–DFLASH–8/08
AT25DF081
2. Pin Descriptions and Pinouts
Table 2-1.
Symbol
Pin Descriptions
Name and Function
CHIP SELECT:
Asserting the CS pin selects the device. When the CS pin is deasserted, the
device will be deselected and normally be placed in standby mode (not Deep Power-Down mode),
and the SO pin will be in a high-impedance state. When the device is deselected, data will not be
accepted on the SI pin.
A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition
is required to end an operation. When ending an internally self-timed operation such as a program
or erase cycle, the device will not enter the standby mode until the completion of the operation.
SERIAL CLOCK:
This pin is used to provide a clock to the device and is used to control the flow of
data to and from the device. Command, address, and input data present on the SI pin is always
latched on the rising edge of SCK, while output data on the SO pin is always clocked out on the
falling edge of SCK.
SERIAL INPUT:
The SI pin is used to shift data into the device. The SI pin is used for all data input
including command and address sequences. Data on the SI pin is always latched on the rising
edge of SCK.
SERIAL OUTPUT:
The SO pin is used to shift data out from the device. Data on the SO pin is
always clocked out on the falling edge of SCK.
WRITE PROTECT:
The WP pin controls the hardware locking feature of the device. Please refer to
“Protection Commands and Features” on page 12
for more details on protection features and the
WP pin.
The WP pin is internally pulled-high and may be left floating if hardware controlled protection will
not be used. However, it is recommended that the WP pin also be externally connected to V
CC
whenever possible.
HOLD:
The HOLD pin is used to temporarily pause serial communication without deselecting or
resetting the device. While the HOLD pin is asserted, transitions on the SCK pin and data on the SI
pin will be ignored, and the SO pin will be in a high-impedance state.
The CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold
condition to start. A Hold condition pauses serial communication only and does not have an effect
on internally self-timed operations such as a program or erase cycle. Please refer to
“Hold” on
page 27
for additional details on the Hold operation.
The HOLD pin is internally pulled-high and may be left floating if the Hold function will not be used.
However, it is recommended that the HOLD pin also be externally connected to V
CC
whenever
possible.
DEVICE POWER SUPPLY:
The V
CC
pin is used to supply the source voltage to the device.
Operations at invalid V
CC
voltages may produce spurious results and should not be attempted.
GROUND:
The ground reference for the power supply. GND should be connected to the system
ground.
Asserted
State
Type
CS
Low
Input
SCK
Input
SI
Input
SO
Output
WP
Low
Input
HOLD
Low
Input
V
CC
GND
Power
Power
3
3674E–DFLASH–8/08
Figure 2-1.
CS
SO
WP
GND
1
2
3
4
8-SOIC Top View
8
7
6
5
VCC
HOLD
SCK
SI
Figure 2-2.
CS
SO
WP
GND
1
2
3
4
8-UDFN Top View
VCC
7
HOLD
6
SCK
5
SI
8
Figure 2-3.
11-dBGA (Top View
Through Back of Die)
1
A
NC
B
VCC CS
C
HOLD SO
D
SCK WP
E
SI GND
F
NC
NC
2
3
4
3. Block Diagram
CS
CONTROL AND
PROTECTION LOGIC
I/O BUFFERS
AND LATCHES
SCK
SI
SO
SRAM
DATA BUFFER
INTERFACE
CONTROL
AND
LOGIC
ADDRESS LATCH
Y-DECODER
Y-GATING
WP
HOLD
X-DECODER
FLASH
MEMORY
ARRAY
4. Memory Array
To provide the greatest flexibility, the memory array of the AT25DF081 can be erased in four lev-
els of granularity including a full chip erase. In addition, the array has been divided into physical
sectors of uniform size, of which each sector can be individually protected from program and
erase operations. The size of the physical sectors is optimized for both code and data storage
applications, allowing both code and data segments to reside in their own isolated
regions.
Figure 4-1 on page 5
illustrates the breakdown of each erase level as well as the break-
down of each physical sector.
4
AT25DF081
3674E–DFLASH–8/08
AT25DF081
Figure 4-1.
Memory Architecture Diagram
Block Erase Detail
Internal Sectoring for
Sector Protection
Function
64KB
Block Erase
(D8h Command)
32KB
Block Erase
(52h Command)
4KB
Block Erase
(20h Command)
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
•••
Page Program Detail
Block Address
Range
0F F F F F h – 0F F 000h
0F E F F F h– 0F E 000h
0F DF F F h – 0F D000h
0F CF F F h – 0F C000h
0F BF F F h – 0F B000h
0F AF F F h – 0F A000h
0F 9F F F h – 0F 9000h
0F 8F F F h – 0F 8000h
0F 7F F F h – 0F 7000h
0F 6F F F h – 0F 6000h
0F 5F F F h – 0F 5000h
0F 4F F F h – 0F 4000h
0F 3F F F h – 0F 3000h
0F 2F F F h – 0F 2000h
0F 1F F F h – 0F 1000h
0F 0F F F h – 0F 0000h
0E F F F F h– 0E F 000h
0E E F F F h– 0E E 000h
0E DF F F h – 0E D000h
0E CF F F h– 0E C000h
0E BF F F h– 0E B000h
0E AF F F h – 0E A000h
0E 9F F F h – 0E 9000h
0E 8F F F h – 0E 8000h
0E 7F F F h – 0E 7000h
0E 6F F F h – 0E 6000h
0E 5F F F h – 0E 5000h
0E 4F F F h – 0E 4000h
0E 3F F F h – 0E 3000h
0E 2F F F h – 0E 2000h
0E 1F F F h – 0E 1000h
0E 0F F F h – 0E 0000h
1-256 Byte
Page Program
(02h Command)
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
•••
Page Address
Range
0F F F F F h – 0F F F 00h
0F F E F F h– 0F F E 00h
0F F DF F h – 0F F D00h
0F F CF F h – 0F F C00h
0F F BF F h – 0F F B00h
0F F AF F h – 0F F A00h
0F F 9F F h – 0F F 900h
0F F 8F F h – 0F F 800h
0F F 7F F h – 0F F 700h
0F F 6F F h – 0F F 600h
0F F 5F F h – 0F F 500h
0F F 4F F h – 0F F 400h
0F F 3F F h – 0F F 300h
0F F 2F F h – 0F F 200h
0F F 1F F h – 0F F 100h
0F F 0F F h – 0F F 000h
0F E F F F h– 0F E F 00h
0F E E F F h– 0F E E 00h
0F E DF F h – 0F E D00h
0F E CF F h– 0F E C00h
0F E BF F h– 0F E B00h
0F E AF F h – 0F E A00h
0F E 9F F h – 0F E 900h
0F E 8F F h – 0F E 800h
32KB
64KB
(Sector 15)
64KB
32KB
32KB
64KB
(Sector 14)
64KB
32KB
32KB
64KB
(Sector 0)
64KB
32KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
00F F F F h – 00F 000h
00E F F F h – 00E 000h
00DF F F h – 00D000h
00CF F F h – 00C000h
00BF F F h – 00B000h
00AF F F h – 00A000h
009F F F h – 009000h
008F F F h – 008000h
007F F F h – 007000h
006F F F h – 006000h
005F F F h – 005000h
004F F F h – 004000h
003F F F h – 003000h
002F F F h – 002000h
001F F F h – 001000h
000F F F h – 000000h
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
0017F F h – 001700h
0016F F h – 001600h
0015F F h – 001500h
0014F F h – 001400h
0013F F h – 001300h
0012F F h – 001200h
0011F F h – 001100h
0010F F h – 001000h
000F F F h – 000F 00h
000E F F h – 000E 00h
000DF F h – 000D00h
000CF F h – 000C00h
000BF F h – 000B00h
000AF F h – 000A00h
0009F F h – 000900h
0008F F h – 000800h
0007F F h – 000700h
0006F F h – 000600h
0005F F h – 000500h
0004F F h – 000400h
0003F F h – 000300h
0002F F h – 000200h
0001F F h – 000100h
0000F F h – 000000h
•••
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•••
5
3674E–DFLASH–8/08
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