AT45DB041D-MU datasheet, PDF - EEWORLD Datasheet

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AT45DB041D-MU: Description4M X 1 FLASH 2.7V PROM, DSO8; Categorystorage storage; File Size1MB，53 Pages; ManufacturerAtmel (Microchip); Environmental Compliance

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AT45DB041D-MU Overview

4M X 1 FLASH 2.7V PROM, DSO8

AT45DB041D-MU Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Atmel (Microchip)
Parts packaging code	SON
package instruction	VSON, SOLCC8,.25
Contacts	8
Reach Compliance Code	compli
ECCN code	EAR99
Samacsys Descripti	NOR Flash 4-megabit 2.5-volt or 2.7-volt DataFlash AT45DB041D
Other features	ORGANIZED AS 2048 PAGES OF 264 BYTES EACH
Maximum clock frequency (fCLK)	66 MHz
Data retention time - minimum	20
Durability	100000 Write/Erase Cycles
JESD-30 code	R-XDSO-N8
JESD-609 code	e3
length	6 mm
memory density	4194304 bi
Memory IC Type	FLASH
memory width	1
Number of functions	1
Number of terminals	8
word count	4194304 words
character code	4000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	4MX1
Package body material	UNSPECIFIED
encapsulated code	VSON
Encapsulate equivalent code	SOLCC8,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, VERY THIN PROFILE
Parallel/Serial	SERIAL
Peak Reflow Temperature (Celsius)	260
power supply	3/3.3 V
Programming voltage	2.7 V
Certification status	Not Qualified
Maximum seat height	0.6 mm
Serial bus type	SPI
Maximum standby current	0.00001 A
Maximum slew rate	0.017 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	MATTE TIN
Terminal form	NO LEAD
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	40
type	NOR TYPE
width	5 mm
write protect	HARDWARE/SOFTWARE

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Features

•

Single 2.5V or 2.7V to 3.6V Supply

•

RapidS

Serial Interface: 66 MHz Maximum Clock Frequency

•

– SPI Compatible Modes 0 and 3

User Configurable Page Size

– 256 Bytes per Page

– 264 Bytes per Page

– Page Size Can Be Factory Pre-configured for 256 Bytes

Page Program Operation

– Intelligent Programming Operation

– 2,048 Pages (256/264 Bytes/Page) Main Memory

Flexible Erase Options

– Page Erase (256 Bytes)

– Block Erase (2 Kbytes)

– Sector Erase (64 Kbytes)

– Chip Erase (4 Mbits)

Two SRAM Data Buffers (256/264 Bytes)

– Allows Receiving of Data while Reprogramming the Flash Array

Continuous Read Capability through Entire Array

– Ideal for Code Shadowing Applications

Low-power Dissipation

– 7 mA Active Read Current Typical

– 25 µA Standby Current Typical

– 5 µA Deep Power-down Typical

Hardware and Software Data Protection Features

– Individual Sector

Sector Lockdown for Secure Code and Data Storage

– Individual Sector

Security: 128-byte Security Register

– 64-byte User Programmable Space

– Unique 64-byte Device Identifier

JEDEC Standard Manufacturer and Device ID Read

100,000 Program/Erase Cycles Per Page Minimum

Data Retention – 20 Years

Industrial Temperature Range

Green (Pb/Halide-free/RoHS Compliant) Packaging Options

•

4-megabit

2.5-volt or

2.7-volt

DataFlash

AT45DB041D

•

1. Description

The AT45DB041D is a 2.5V or 2.7V, serial-interface Flash memory ideally suited for a

wide variety of digital voice-, image-, program code- and data-storage applications.

The AT45DB041D supports RapidS serial interface for applications requiring very

high speed operations. RapidS serial interface is SPI compatible for frequencies up to

66 MHz. Its 4,325,376 bits of memory are organized as 2,048 pages of 256 bytes or

264 bytes each. In addition to the main memory, the AT45DB041D also contains two

SRAM buffers of 256/264 bytes each. The buffers allow the receiving of data while a

page in the main Memory is being reprogrammed, as well as writing a continuous data

stream. EEPROM emulation (bit or byte alterability) is easily handled with a self-con-

tained three step read-modify-write operation. Unlike conventional Flash memories

that are accessed randomly with multiple address lines and a parallel interface, the

DataFlash uses a RapidS serial interface to sequentially access its data. The simple

sequential access dramatically reduces active pin count, facilitates hardware layout,

3595L–DFLASH–4/08

increases system reliability, minimizes switching noise, and reduces package size. The device is

optimized for use in many commercial and industrial applications where high-density, low-pin

count, low-voltage and low-power are essential.

To allow for simple in-system reprogrammability, the AT45DB041D does not require high input

voltages for programming. The device operates from a single power supply, 2.5V to 3.6V or 2.7V

to 3.6V, for both the program and read operations. The AT45DB041D is enabled through the

chip select pin (CS) and accessed via a three-wire interface consisting of the Serial Input (SI),

Serial Output (SO), and the Serial Clock (SCK).

All programming and erase cycles are self-timed.

2. Pin Configurations and Pinouts

Table 2-1.

Symbol

Pin Configurations

Asserted

State

Type

Name and Function

Chip Select:

Asserting the CS pin selects the device. When the CS pin is deasserted, the device will be deselected

and normally be placed in the standby mode (not Deep Power-Down mode), and the output pin (SO) will be in a

high-impedance state. When the device is deselected, data will not be accepted on the input pin (SI).

A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition is required to

end an operation. When ending an internally self-timed operation such as a program or erase cycle, the device

will not enter the standby mode until the completion of the operation.

Serial Clock:

This pin is used to provide a clock to the device and is used to control the flow of data to and from

the device. Command, address, and input data present on the SI pin is always latched on the rising edge of SCK,

while output data on the SO pin is always clocked out on the falling edge of SCK.

Serial Input:

The SI pin is used to shift data into the device. The SI pin is used for all data input including

command and address sequences. Data on the SI pin is always latched on the rising edge of SCK.

Serial Output:

The SO pin is used to shift data out from the device. Data on the SO pin is always clocked out on

the falling edge of SCK.

Write Protect:

When the WP pin is asserted, all sectors specified for protection by the Sector Protection Register will

be protected against program and erase operations regardless of whether the Enable Sector Protection command

has been issued or not. The WP pin functions independently of the software controlled protection method. After the

WP pin goes low, the content of the Sector Protection Register cannot be modified.

Low

Input

SCK

–

Input

–

Input

Output

If a program or erase command is issued to the device while the WP pin is asserted, the device will simply ignore

the command and perform no operation. The device will return to the idle state once the CS pin has been

deasserted. The Enable Sector Protection command and Sector Lockdown command, however, will be

recognized by the device when the WP pin is asserted.

The WP pin is internally pulled-high and may be left floating if hardware controlled protection will not be used.

However, it is recommended that the WP pin also be externally connected to V

whenever possible.

Reset:

A low state on the reset pin (RESET) will terminate the operation in progress and reset the internal state

machine to an idle state. The device will remain in the reset condition as long as a low level is present on the RESET

pin. Normal operation can resume once the RESET pin is brought back to a high level.

The device incorporates an internal power-on reset circuit, so there are no restrictions on the RESET pin during

power-on sequences. If this pin and feature are not utilized it is recommended that the RESET pin be driven high

externally.

Device Power Supply:

The V

pin is used to supply the source voltage to the device.

Operations at invalid V

voltages may produce spurious results and should not be attempted.

Ground:

The ground reference for the power supply. GND should be connected to the system ground.

Low

Input

RESET

Low

Input

GND

–

Power

Ground

AT45DB041D

3595L–DFLASH–4/08

AT45DB041D

6. Read Commands

By specifying the appropriate opcode, data can be read from the main memory or from either

one of the two SRAM data buffers. The DataFlash supports RapidS protocols for Mode 0 and

Mode 3. Please refer to the “Detailed Bit-level Read Timing” diagrams in this datasheet for

details on the clock cycle sequences for each mode.

6.1

Continuous Array Read (Legacy Command – E8H): Up to 66 MHz

By supplying an initial starting address for the main memory array, the Continuous Array Read

command can be utilized to sequentially read a continuous stream of data from the device by

simply providing a clock signal; no additional addressing information or control signals need to

be provided. The DataFlash incorporates an internal address counter that will automatically

increment on every clock cycle, allowing one continuous read operation without the need of

additional address sequences. To perform a continuous read from the DataFlash standard page

size (264 bytes), an opcode of E8H must be clocked into the device followed by three address

bytes (which comprise the 24-bit page and byte address sequence) and 4 don’t care bytes. The

first 11 bits (PA10 - PA0) of the 20-bit address sequence specify which page of the main mem-

ory array to read, and the last 9 bits (BA8 - BA0) of the 20-bit address sequence specify the

starting byte address within the page. To perform a continuous read from the binary page size

(256 bytes), the opcode (E8H) must be clocked into the device followed by three address bytes

and 4 don’t care bytes. The first 11 bits (A18 - A8) of the 19-bits sequence specify which page of

the main memory array to read, and the last 8 bits (A7 - A0) of the 19-bits address sequence

specify the starting byte address within the page. The don’t care bytes that follow the address

bytes are needed to initialize the read operation. Following the don’t care bytes, additional clock

pulses on the SCK pin will result in data being output on the SO (serial output) pin.

The CS pin must remain low during the loading of the opcode, the address bytes, the don’t care

bytes, and the reading of data. When the end of a page in main memory is reached during a

Continuous Array Read, the device will continue reading at the beginning of the next page with

no delays incurred during the page boundary crossover (the crossover from the end of one page

to the beginning of the next page). When the last bit in the main memory array has been read,

the device will continue reading back at the beginning of the first page of memory. As with cross-

ing over page boundaries, no delays will be incurred when wrapping around from the end of the

array to the beginning of the array.

A low-to-high transition on the CS pin will terminate the read operation and tri-state the output

pin (SO). The maximum SCK frequency allowable for the Continuous Array Read is defined by

the f

CAR1

specification. The Continuous Array Read bypasses both data buffers and leaves the

contents of the buffers unchanged.

6.2

Continuous Array Read (High Frequency Mode – 0BH): Up to 66 MHz

This command can be used with the serial interface to read the main memory array sequentially

in high speed mode for any clock frequency up to the maximum specified by f

CAR1

. To perform a

continuous read array with the page size set to 264 bytes, the CS must first be asserted then an

opcode 0BH must be clocked into the device followed by three address bytes and a dummy

byte. The first 11 bits (PA10 - PA0) of the 20-bit address sequence specify which page of the

main memory array to read, and the last 9 bits (BA8 - BA0) of the 20-bit address sequence spec-

ify the starting byte address within the page. To perform a continuous read with the page size

set to 256 bytes, the opcode, 0BH, must be clocked into the device followed by three address

bytes (A18 - A0) and a dummy byte. Following the dummy byte, additional clock pulses on the

SCK pin will result in data being output on the SO (serial output) pin.

3595L–DFLASH–4/08

AT45DB041D-MU Related Products

	AT45DB041D-MU	AT45DB041D-MU-SL954	AT45DB041D_08	AT45DB041D-MU-SL955
Description	4M X 1 FLASH 2.7V PROM, DSO8	4M X 1 FLASH 2.7V PROM, DSO8	4M X 1 FLASH 2.7V PROM, DSO8	4M X 1 FLASH 2.7V PROM, DSO8
memory width	1	1	1	1
Number of functions	1	1	1	1
Number of terminals	8	8	8	8
Maximum operating temperature	85 °C	85 °C	85 Cel	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 Cel	-40 °C
organize	4MX1	4MX1	4M X 1	4MX1
surface mount	YES	YES	Yes	YES
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	NO LEAD	NO LEAD	NO LEAD	NO LEAD
Terminal location	DUAL	DUAL	DUAL	DUAL
Is it Rohs certified?	conform to	conform to	-	conform to
Maker	Atmel (Microchip)	Atmel (Microchip)	-	Atmel (Microchip)
Parts packaging code	SON	SON	-	SON
package instruction	VSON, SOLCC8,.25	VSON, SOLCC8,.25	-	VSON, SOLCC8,.25
Contacts	8	8	-	8
Reach Compliance Code	compli	compli	-	unknow
ECCN code	EAR99	EAR99	-	EAR99
Other features	ORGANIZED AS 2048 PAGES OF 264 BYTES EACH	ORGANIZED AS 2048 PAGES OF 256 BYTES EACH	-	ORGANIZED AS 2048 PAGES OF 256 BYTES EACH
Maximum clock frequency (fCLK)	66 MHz	66 MHz	-	66 MHz
Data retention time - minimum	20	20	-	20
Durability	100000 Write/Erase Cycles	100000 Write/Erase Cycles	-	100000 Write/Erase Cycles
JESD-30 code	R-XDSO-N8	R-XDSO-N8	-	R-XDSO-N8
JESD-609 code	e3	e3	-	e3
length	6 mm	6 mm	-	6 mm
memory density	4194304 bi	4194304 bi	-	4194304 bi
Memory IC Type	FLASH	FLASH	-	FLASH
word count	4194304 words	4194304 words	-	4194304 words
character code	4000000	4000000	-	4000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	-	SYNCHRONOUS
Package body material	UNSPECIFIED	UNSPECIFIED	-	UNSPECIFIED
encapsulated code	VSON	VSON	-	VSON
Encapsulate equivalent code	SOLCC8,.25	SOLCC8,.25	-	SOLCC8,.25
Package shape	RECTANGULAR	RECTANGULAR	-	RECTANGULAR
Package form	SMALL OUTLINE, VERY THIN PROFILE	SMALL OUTLINE, VERY THIN PROFILE	-	SMALL OUTLINE, VERY THIN PROFILE
Parallel/Serial	SERIAL	SERIAL	-	SERIAL
power supply	3/3.3 V	3/3.3 V	-	3/3.3 V
Programming voltage	2.7 V	2.7 V	-	2.7 V
Certification status	Not Qualified	Not Qualified	-	Not Qualified
Maximum seat height	0.6 mm	0.6 mm	-	0.6 mm
Serial bus type	SPI	SPI	-	SPI
Maximum standby current	0.00001 A	0.00001 A	-	0.00001 A
Maximum slew rate	0.017 mA	0.017 mA	-	0.017 mA
Maximum supply voltage (Vsup)	3.6 V	3.6 V	-	3.6 V
Minimum supply voltage (Vsup)	2.7 V	2.7 V	-	2.7 V
Nominal supply voltage (Vsup)	3 V	3 V	-	3 V
technology	CMOS	CMOS	-	CMOS
Terminal surface	MATTE TIN	MATTE TIN	-	MATTE TIN
Terminal pitch	1.27 mm	1.27 mm	-	1.27 mm
type	NOR TYPE	NOR TYPE	-	NOR TYPE
width	5 mm	5 mm	-	5 mm
write protect	HARDWARE/SOFTWARE	HARDWARE/SOFTWARE	-	HARDWARE/SOFTWARE

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