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AT89C51CC01: DescriptionEnhanced 8-bit Microcontroller with CAN Controller and Flash Memory; File Size1MB，167 Pages; ManufacturerAtmel (Microchip)

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AT89C51CC01 Overview

Enhanced 8-bit Microcontroller with CAN Controller and Flash Memory

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Features

•

80C51 Core Architecture

256 Bytes of On-chip RAM

1K Bytes of On-chip XRAM

32K Bytes of On-chip Flash Memory

– Data Retention: 10 Years at 85°

Erase/Write Cycle: 100K

Boot Code Section with Independent Lock Bits

2K Bytes of On-chip Flash for Bootloader

In-System Programming by On-Chip Boot Program (CAN, UART) and IAP Capability

2K Bytes of On-chip EEPROM

Erase/Write Cycle: 100K

14-sources 4-level Interrupts

Three 16-bit Timers/Counters

Full Duplex UART Compatible 80C51

Maximum Crystal Frequency 40 MHz, in X2 Mode, 20 MHz (CPU Core, 20 MHz)

Five Ports: 32 + 2 Digital I/O Lines

Five-channel 16-bit PCA with:

– PWM (8-bit)

– High-speed Output

– Timer and Edge Capture

Double Data Pointer

21-bit Watchdog Timer (7 Programmable Bits)

A 10-bit Resolution Analog to Digital Converter (ADC) with 8 Multiplexed Inputs

Full CAN Controller:

– Fully Compliant with CAN Rev2.0A and 2.0B

– Optimized Structure for Communication Management (Via SFR)

– 15 Independent Message Objects:

Each Message Object Programmable on Transmission or Reception

Individual Tag and Mask Filters up to 29-bit Identifier/Channel

8-byte Cyclic Data Register (FIFO)/Message Object

16-bit Status and Control Register/Message Object

16-bit Time-Stamping Register/Message Object

CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message

Object

Access to Message Object Control and Data Registers Via SFR

Programmable Reception Buffer Length Up To 15 Message Objects

Priority Management of Reception of Hits on Several Message Objects at the

Same Time (Basic CAN Feature)

Priority Management for Transmission

Message Object Overrun Interrupt

– Supports:

Time Triggered Communication

Autobaud and Listening Mode

Programmable Automatic Reply Mode

– 1-Mbit/s Maximum Transfer Rate at 8 MHz

(1)

Crystal Frequency in X2 Mode

– Readable Error Counters

– Programmable Link to On-chip Timer for Time Stamping and Network

Synchronization

– Independent Baud Rate Prescaler

– Data, Remote, Error and Overload Frame Handling

On-chip Emulation Logic (Enhanced Hook System)

Power Saving Modes:

– Idle Mode

– Power-down Mode

Enhanced 8-bit

Microcontroller

with CAN

Controller and

Flash Memory

•

T89C51CC01

AT89C51CC01

•

At BRP = 1 sampling point will be fixed.

Rev. 4129N–CAN–03/08

I/O Configurations

Each Port SFR operates via type-D latches, as illustrated in Figure 1 for Ports 3 and 4. A

CPU "write to latch" signal initiates transfer of internal bus data into the type-D latch. A

CPU "read latch" signal transfers the latched Q output onto the internal bus. Similarly, a

"read pin" signal transfers the logical level of the Port pin. Some Port data instructions

activate the "read latch" signal while others activate the "read pin" signal. Latch instruc-

tions are referred to as Read-Modify-Write instructions. Each I/O line may be

independently programmed as input or output.

Port 1, Port 3 and Port 4

Figure 1 shows the structure of Ports 1 and 3, which have internal pull-ups. An external

source can pull the pin low. Each Port pin can be configured either for general-purpose

I/O or for its alternate input output function.

To use a pin for general-purpose output, set or clear the corresponding bit in the Px reg-

ister (x = 1,3 or 4). To use a pin for general-purpose input, set the bit in the Px register.

This turns off the output FET drive.

To configure a pin for its alternate function, set the bit in the Px register. When the latch

is set, the "alternate output function" signal controls the output level (see Figure 1). The

operation of Ports 1, 3 and 4 is discussed further in the "quasi-Bidirectional Port Opera-

tion" section.

Figure 1.

Port 1, Port 3 and Port 4 Structure

VCC

ALTERNATE

OUTPUT

FUNCTION

INTERNAL

PULL-UP (1)

READ

LATCH

INTERNAL

BUS

WRITE

LATCH

D P1.X Q

P3.X

P4.X

LATCH

P1.x

P3.x

P4.x

READ

ALTERNATE

INPUT

FUNCTION

Note:

The internal pull-up can be disabled on P1 when analog function is selected.

Port 0 and Port 2

Ports 0 and 2 are used for general-purpose I/O or as the external address/data bus. Port

0, shown in Figure 3, differs from the other Ports in not having internal pull-ups. Figure 3

shows the structure of Port 2. An external source can pull a Port 2 pin low.

To use a pin for general-purpose output, set or clear the corresponding bit in the Px reg-

ister (x = 0 or 2). To use a pin for general-purpose input, set the bit in the Px register to

turn off the output driver FET.

A/T89C51CC01

4129N–CAN–03/08

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	AT89C51CC01	T89C51CC01	T89C51CC01_08	T89C51CC01UA-7CTIM	T89C51CC01CA-7CTIM	T89C51CC01CA-RLTIM	T89C51CC01UA-SLSIM	T89C51CC01UA-RLTIM	T89C51CC01CA-SLSIM
Description	Enhanced 8-bit Microcontroller with CAN Controller and Flash Memory	Enhanced 8-bit Microcontroller with CAN Controller and Flash Memory	Enhanced 8-bit Microcontroller with CAN Controller and Flash Memory	Enhanced 8-bit Microcontroller with CAN Controller and Flash Memory	Enhanced 8-bit Microcontroller with CAN Controller and Flash Memory	Enhanced 8-bit Microcontroller with CAN Controller and Flash Memory	Enhanced 8-bit Microcontroller with CAN Controller and Flash Memory	Enhanced 8-bit Microcontroller with CAN Controller and Flash Memory	Enhanced 8-bit Microcontroller with CAN Controller and Flash Memory
Is it Rohs certified?	-	-	-	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Maker	-	-	-	Atmel (Microchip)	Atmel (Microchip)	Atmel (Microchip)	Atmel (Microchip)	Atmel (Microchip)	Atmel (Microchip)
Parts packaging code	-	-	-	BGA	BGA	QFP	LCC	QFP	LCC
package instruction	-	-	-	LFBGA, BGA64(UNSPEC)	LFBGA, BGA64(UNSPEC)	LQFP, QFP44,.47SQ,32	QCCJ, LDCC44,.7SQ	LQFP, QFP44,.47SQ,32	QCCJ, LDCC44,.7SQ
Contacts	-	-	-	64	64	44	44	44	44
Reach Compliance Code	-	-	-	unknow	compli	unknow	unknow	unknow	unknow
ECCN code	-	-	-	3A991.A.2	3A991.A.2	3A991.A.2	3A991.A.2	3A991.A.2	3A991.A.2
Has ADC	-	-	-	YES	YES	YES	YES	YES	YES
Address bus width	-	-	-	16	16	16	16	16	16
bit size	-	-	-	8	8	8	8	8	8
CPU series	-	-	-	8051	8051	8051	8051	8051	8051
maximum clock frequency	-	-	-	40 MHz	40 MHz	40 MHz	40 MHz	40 MHz	40 MHz
DAC channel	-	-	-	NO	NO	NO	NO	NO	NO
DMA channel	-	-	-	NO	NO	NO	NO	NO	NO
External data bus width	-	-	-	8	8	8	8	8	8
JESD-30 code	-	-	-	S-PBGA-B64	S-PBGA-B64	S-PQFP-G44	S-PQCC-J44	S-PQFP-G44	S-PQCC-J44
JESD-609 code	-	-	-	e0	e0	e0	e0	e0	e0
length	-	-	-	8 mm	8 mm	10 mm	16.5481 mm	10 mm	16.5481 mm
Number of I/O lines	-	-	-	34	34	34	34	34	34
Number of terminals	-	-	-	64	64	44	44	44	44
Maximum operating temperature	-	-	-	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-	-	-	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
PWM channel	-	-	-	YES	YES	YES	YES	YES	YES
Package body material	-	-	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	-	-	-	LFBGA	LFBGA	LQFP	QCCJ	LQFP	QCCJ
Encapsulate equivalent code	-	-	-	BGA64(UNSPEC)	BGA64(UNSPEC)	QFP44,.47SQ,32	LDCC44,.7SQ	QFP44,.47SQ,32	LDCC44,.7SQ
Package shape	-	-	-	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	-	-	-	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE	CHIP CARRIER	FLATPACK, LOW PROFILE	CHIP CARRIER
Peak Reflow Temperature (Celsius)	-	-	-	NOT SPECIFIED	240	NOT SPECIFIED	225	NOT SPECIFIED	225
power supply	-	-	-	5 V	5 V	5 V	5 V	5 V	5 V
Certification status	-	-	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
RAM (bytes)	-	-	-	256	256	256	256	256	256
rom(word)	-	-	-	32768	32768	32768	32768	32768	32768
ROM programmability	-	-	-	FLASH	FLASH	FLASH	FLASH	FLASH	FLASH
Maximum seat height	-	-	-	1.5 mm	1.5 mm	1.6 mm	4.57 mm	1.6 mm	4.57 mm
speed	-	-	-	40 MHz	40 MHz	40 MHz	40 MHz	40 MHz	40 MHz
Maximum supply voltage	-	-	-	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage	-	-	-	3 V	3 V	3 V	3 V	3 V	3 V
Nominal supply voltage	-	-	-	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	-	-	-	YES	YES	YES	YES	YES	YES
technology	-	-	-	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	-	-	-	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	-	-	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	-	-	-	BALL	BALL	GULL WING	J BEND	GULL WING	J BEND
Terminal pitch	-	-	-	0.8 mm	0.8 mm	0.8 mm	1.27 mm	0.8 mm	1.27 mm
Terminal location	-	-	-	BOTTOM	BOTTOM	QUAD	QUAD	QUAD	QUAD
Maximum time at peak reflow temperature	-	-	-	NOT SPECIFIED	30	NOT SPECIFIED	30	NOT SPECIFIED	30
width	-	-	-	8 mm	8 mm	10 mm	16.5481 mm	10 mm	16.5481 mm
uPs/uCs/peripheral integrated circuit type	-	-	-	MICROCONTROLLER	MICROCONTROLLER	MICROCONTROLLER	MICROCONTROLLER	MICROCONTROLLER	MICROCONTROLLER

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