Features
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80C51 Core Architecture
256 Bytes of On-chip RAM
256 Bytes of On-chip XRAM
16K Bytes of On-chip Flash Memory
– Data Retention: 10 Years at 85°C
– Erase/Write Cycle: 100K
Boot Code Section with Independent Lock Bits
2K Bytes of On-chip Flash for Bootloader
In-System Programming by On-Chip Boot Program (CAN, UART) and IAP Capability
2K Bytes of On-chip EEPROM
– Erase/Write Cycle: 100K
14-sources 4-level Interrupts
Three 16-bit Timers/Counters
Full Duplex UART Compatible 80C51
Maximum Crystal Frequency 40 MHz. In X2 Mode, 20 MHz (CPU Core, 40 MHz)
Three or Four Ports: 16 or 20 Digital I/O Lines
Two-channel 16-bit PCA
– PWM (8-bit)
– High-speed Output
– Timer and Edge Capture
Double Data Pointer
21-bit Watchdog Timer (7 Programmable bits)
A 10-bit Resolution Analog-to-Digital Converter (ADC) with 8 Multiplexed Inputs
Full CAN Controller
– Fully Compliant with CAN rev.# 2.0A and 2.0B
– Optimized Structure for Communication Management (Via SFR)
– 4 Independent Message Objects
-Each Message Object Programmable on Transmission or Reception
-Individual Tag and Mask Filters up to 29-bit Identifier/Channel
-8-byte Cyclic Data Register (FIFO)/Message Object
-16-bit Status and Control Register/Message Object
-16-bit Time-Stamping Register/Message Object
-CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message
Object
-Access to Message Object Control and Data Registers Via SFR
-Programmable Reception Buffer Length up to 4 Message Objects
-Priority Management of Reception of Hits on Several Message Objects
Simultaneously (Basic CAN Feature)
-Priority Management for Transmission
-Message Object Overrun Interrupt
– Supports
-Time Triggered Communication
-Autobaud and Listening Mode
-Programmable Automatic Reply Mode
1-Mbit/s Maximum Transfer Rate at 8 MHz
(1)
Crystal Frequency In X2 Mode
Readable Error Counters
Programmable Link to On-chip Timer for Time Stamping and Network Synchronization
Independent Baud Rate Prescaler
Data, Remote, Error and Overload Frame Handling
Power-saving Modes
– Idle Mode
– Power-down Mode
Power Supply: 3 Volts to 5.5 Volts
Temperature Range: Industrial (-40° to +85°C)
Packages: SOIC28, SOIC24, PLCC28, VQFP32
1. At BRP = 1 sampling point will be fixed.
Enhanced 8-bit
Microcontroller
with CAN
Controller and
Flash
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T89C51CC02
AT89C51CC02
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Note:
Rev. 4126L–CAN–01/08
Description
Part of the CANary
TM
family of 8-bit microcontrollers dedicated to CAN network applica-
tions, the T89C51CC02 is a low-pin count 8-bit Flash microcontroller.
In X2 Mode a maximum external clock rate of 20 MHz reaches a 300 ns cycle time.
Besides the full CAN controller T89C51CC02 provides 16K Bytes of Flash memory
including In-System Programming (ISP), 2K Bytes Boot Flash Memory, 2K Bytes
EEPROM and 512 Bytes RAM.
Special attention is payed to the reduction of the electro-magnetic emission of
T89C51CC02.
Block Diagram
RxDC
VAVCC
VAGND
T2EX
RxD
TxD
Vcc
Vss
PCA
ECI
T2
TxDC
UART
RAM
256x8
Flash Boot
EE
16K x loader PROM
8
2K x 8 2K x 8
XRAM
256 x 8
PCA
Timer 2
CAN
CONTROLLER
XTAL1
XTAL2
CPU
C51
CORE
IB-bus
Timer 0
Timer 1
INT
Ctrl
Parallel I/O Ports
Port 1 Port 2 Port 3 Port 4
Watch
Dog
10-bit
ADC
RESET
Note:
1. 8 analog Inputs/8 Digital I/O.
2. 2-bit I/O Port.
2
AT/T89C51CC02
4126L–CAN–01/08
VAREF
T0
T1
INT0
INT1
P1(1)
P2(2)
P4(2)
P3
AT/T89C51CC02
Pin Description
Pin Name
Type
Description
VSS
VCC
VAREF
VAVCC
VAGND
P1.0:7
GND
Circuit ground
Supply Voltage
Reference Voltage for ADC (input)
Supply Voltage for ADC
Reference Ground for ADC (internaly connected with the VSS)
I/O
Port 1:
Is an 8-bit bi-directional I/O port with internal pull-ups. Port 1 pins can be used for digital input/output or as
analog inputs for the Analog Digital Converter (ADC). Port 1 pins that have 1’s written to them are pulled
high by the internal pull-up transistors and can be used as inputs in this state. As inputs, Port 1 pins that
are being pulled low externally will be the source of current (I
IL
, See section ’Electrical Characteristic’)
because of the internal pull-ups. Port 1 pins are assigned to be used as analog inputs via the ADCCF
register (in this case the internal pull-ups are disconnected).
As a secondary digital function, port 1 contains the Timer 2 external trigger and clock input; the PCA
external clock input and the PCA module I/O.
P1.0/AN0/T2
Analog input channel 0,
External clock input for Timer/counter2.
P1.1/AN1/T2EX
Analog input channel 1,
Trigger input for Timer/counter2.
P1.2/AN2/ECI
Analog input channel 2,
PCA external clock input.
P1.3/AN3/CEX0
Analog input channel 3,
PCA module 0 Entry of input/PWM output.
P1.4/AN4/CEX1
Analog input channel 4,
PCA module 1 Entry of input/PWM output.
P1.5/AN5
Analog input channel 5,
P1.6/AN6
Analog input channel 6,
P1.7/AN7
Analog input channel 7,
It can drive CMOS inputs without external pull-ups.
Port 2:
Is an 2-bit bi-directional I/O port with internal pull-ups. Port 2 pins that have 1’s written to them are pulled
high by the internal pull-ups and can be used as inputs in this state. As inputs, Port 2 pins that are being
pulled low externally will be a source of current (IIL, on the datasheet) because of the internal pull-ups.
In the T89C51CC02 Port 2 can sink or source 5mA. It can drive CMOS inputs without external pull-ups.
P2.0:1
I/O
5
4126L–CAN–01/08
FPGA/CPLD
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