Features
•
80C52 Compatible
– 8051 Instruction Compatible
– Six 8-bit I/O Ports (64 Pins or 68 Pins Versions)
– Four 8-bit I/O Ports (44 Pins Version)
– Three 16-bit Timer/Counters
– 256 Bytes Scratch Pad RAM
– 9 Interrupt Sources with 4 Priority Levels
Integrated Power Monitor (POR/PFD) to Supervise Internal Power Supply
ISP (In-System Programming) Using Standard V
CC
Power Supply
2048 Bytes Boot ROM Contains Low Level Flash Programming Routines and a Default
Serial Loader
High-speed Architecture
– In Standard Mode:
• 40 MHz (Vcc 2.7V to 5.5V, both Internal and external code execution)
• 60 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)
– In X2 mode (6 Clocks/machine cycle)
• 20 MHz (Vcc 2.7V to 5.5V, both Internal and external code execution)
• 30 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)
64K Bytes On-chip Flash Program/Data Memory
– Byte and Page (128 Bytes) Erase and Write
– 100k Write Cycles
On-chip 1792 bytes Expanded RAM (XRAM)
– Software Selectable Size (0, 256, 512, 768, 1024, 1792 Bytes)
– 768 Bytes Selected at Reset for T89C51RD2 Compatibility
On-chip 2048 Bytes EEPROM Block for Data Storage (AT89C51ED2 Only)
100K Write Cycles
Dual Data Pointer
Variable Length MOVX for Slow RAM/Peripherals
Improved X2 Mode with Independent Selection for CPU and Each Peripheral
Keyboard Interrupt Interface on Port 1
SPI Interface (Master/Slave Mode)
8-bit Clock Prescaler
16-bit Programmable Counter Array
– High Speed Output
– Compare/Capture
– Pulse Width Modulator
– Watchdog Timer Capabilities
Asynchronous Port Reset
Full-duplex Enhanced UART with Dedicated Internal Baud Rate Generator
Low EMI (Inhibit ALE)
Hardware Watchdog Timer (One-time Enabled with Reset-Out), Power-off Flag
Power Control Modes: Idle Mode, Power-down Mode
Single Range Power Supply: 2.7V to 5.5V
Industrial Temperature Range (-40 to +85°C)
Packages: PLCC44, VQFP44, PLCC68, VQFP64
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8-bit Flash
Microcontroller
AT89C51RD2
AT89C51ED2
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1. Description
AT89C51RD2/ED2 is high performance CMOS Flash version of the 80C51 CMOS single chip 8-
bit microcontroller. It contains a 64-Kbyte Flash memory block for code and for data.
The 64-Kbytes Flash memory can be programmed either in parallel mode or in serial mode with
the ISP capability or with software. The programming voltage is internally generated from the
standard V
CC
pin.
The AT89C51RD2/ED2 retains all of the features of the Atmel 80C52 with 256 bytes of internal
RAM, a 9-source 4-level interrupt controller and three timer/counters. The AT89C51ED2 pro-
vides 2048 bytes of EEPROM for nonvolatile data storage.
In addition, the AT89C51RD2/ED2 has a Programmable Counter Array, an XRAM of 1792
bytes, a Hardware Watchdog Timer, SPI interface, Keyboard, a more versatile serial channel
that facilitates multiprocessor communication (EUART) and a speed improvement mechanism
(X2 Mode).
The fully static design of the AT89C51RD2/ED2 allows to reduce system power consumption by
bringing the clock frequency down to any value, including DC, without loss of data.
The AT89C51RD2/ED2 has 2 software-selectable modes of reduced activity and an 8-bit clock
prescaler for further reduction in power consumption. In the Idle mode the CPU is frozen while
the peripherals and the interrupt system are still operating. In the Power-down mode the RAM is
saved and all other functions are inoperative.
The added features of the AT89C51RD2/ED2 make it more powerful for applications that need
pulse width modulation, high speed I/O and counting capabilities such as alarms, motor control,
corded phones, and smart card readers.
Table 1-1.
Memory Size and I/O Pins
Flash (Bytes)
64K
64K
XRAM (Bytes)
1792
1792
Total RAM (Bytes)
2048
2048
I/O
34
50
Package
PLCC44/VQFP44
PLCC68/VQFP64
2
AT89C51RD2/ED2
4235K–8051–05/08
AT89C51RD2/ED2
2. Block Diagram
Figure 2-1.
Block Diagram
T2EX
PCA
Keyboard
(1)
RxD
VCC
TxD
VSS
ECI
(2) (2)
(1)
(1) (1)
(1)
XTALA1
XTALA2
EUART
RAM
256x8
Flash
64K x 8
XRAM
1792 x 8
T2
PCA
Timer2 Keyboard
Watch
-dog
EEPROM*
2K x 8
(AT89C51ED2)
C51
CORE
IB-bus
ALE/ PROG
PSEN
EA
RD
WR
(2)
(2)
CPU
Parallel I/O Ports &
Timer 0
Timer 1
INT
Ctrl
External Bus
Port 0 Port 1
Port 2
Port 3 Port4 Port 5
SPI
BOOT Regulator
2K x 8 POR / PFD
ROM
(2) (2)
RESET
T0
T1
(2) (2)
P1
P2
P0
P3
INT0
INT1
P4
P5
(1) (1)(1)(1)
MISO
MOSI
SCK
SS
(1): Alternate function of Port 1
(2): Alternate function of Port 3
3
4235K–8051–05/08
3. SFR Mapping
The Special Function Registers (SFRs) of the AT89C51RD2/ED2 fall into the following
categories:
• C51 core registers: ACC, B, DPH, DPL, PSW, SP
• I/O port registers: P0, P1, P2, P3, PI2
• Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L,
RCAP2H
• Serial I/O port registers: SADDR, SADEN, SBUF, SCON
• PCA (Programmable Counter Array) registers: CCON, CCAPMx, CL, CH, CCAPxH, CCAPxL
(x: 0 to 4)
• Power and clock control registers: PCON
• Hardware Watchdog Timer registers: WDTRST, WDTPRG
• Interrupt system registers: IE0, IPL0, IPH0, IE1, IPL1, IPH1
• Keyboard Interface registers: KBE, KBF, KBLS
• SPI registers: SPCON, SPSTR, SPDAT
• BRG (Baud Rate Generator) registers: BRL, BDRCON
• Clock Prescaler register: CKRL
• Others: AUXR, AUXR1, CKCON0, CKCON1
Table 3-1.
Mnemonic
ACC
B
PSW
SP
DPL
DPH
C51 Core SFRs
Add
E0h
F0h
D0h
81h
82h
83h
Name
Accumulator
B Register
Program Status Word
Stack Pointer
Data Pointer Low Byte
Data Pointer High Byte
CY
AC
F0
RS1
RS0
OV
F1
P
7
6
5
4
3
2
1
0
Table 3-2.
Mnemonic
PCON
AUXR
AUXR1
CKRL
CKCKON0
CKCKON1
System Management SFRs
Add
87h
8Eh
A2h
97h
8Fh
AFh
Name
Power Control
Auxiliary Register 0
Auxiliary Register 1
Clock Reload Register
Clock Control Register 0
Clock Control Register 1
7
SMOD1
DPU
-
-
-
-
6
SMOD0
-
-
-
WDTX2
-
5
-
M0
ENBOOT
-
PCAX2
-
4
POF
XRS2
-
-
SIX2
-
3
GF1
XRS1
GF3
-
T2X2
-
2
GF0
XRS0
0
-
T1X2
-
1
PD
EXTRAM
-
-
T0X2
-
0
IDL
AO
DPS
-
X2
SPIX2
4
AT89C51RD2/ED2
4235K–8051–05/08
AT89C51RD2/ED2
Table 3-3.
Mnemonic
IEN0
IEN1
IPH0
IPL0
IPH1
IPL1
Interrupt SFRs
Add
A8h
B1h
B7h
B8h
B3h
B2h
Name
Interrupt Enable Control 0
Interrupt Enable Control 1
Interrupt Priority Control High 0
Interrupt Priority Control Low 0
Interrupt Priority Control High 1
Interrupt Priority Control Low 1
7
EA
-
-
-
-
-
6
EC
-
PPCH
PPCL
-
-
5
ET2
-
PT2H
PT2L
-
-
4
ES
-
PHS
PLS
-
-
3
ET1
-
PT1H
PT1L
-
-
2
EX1
ESPI
PX1H
PX1L
SPIH
SPIL
PT0H
PT0L
1
ET0
0
EX0
KBD
PX0H
PX0L
KBDH
KBDL
Table 3-4.
Mnemonic
P0
P1
P2
P3
P4
P5
P5
Port SFRs
Add
80h
90h
A0h
B0h
C0h
E8h
C7h
Name
8-bit Port 0
8-bit Port 1
8-bit Port 2
8-bit Port 3
8-bit Port 4
8-bit Port 5
8-bit Port 5 (byte addressable)
7
6
5
4
3
2
1
0
Table 3-5.
Mnemonic
TCON
TMOD
TL0
TH0
TL1
TH1
WDTRST
WDTPRG
T2CON
T2MOD
RCAP2H
Timer SFRs
Add
88h
89h
8Ah
8Ch
8Bh
8Dh
A6h
A7h
C8h
C9h
CBh
Name
Timer/Counter 0 and 1 Control
Timer/Counter 0 and 1 Modes
Timer/Counter 0 Low Byte
Timer/Counter 0 High Byte
Timer/Counter 1 Low Byte
Timer/Counter 1 High Byte
WatchDog Timer Reset
WatchDog Timer Program
Timer/Counter 2 control
Timer/Counter 2 Mode
Timer/Counter 2 Reload/Capture
High Byte
Timer/Counter 2 Reload/Capture
Low Byte
Timer/Counter 2 High Byte
-
TF2
-
-
EXF2
-
-
RCLK
-
-
TCLK
-
-
EXEN2
-
WTO2
TR2
-
WTO1
C/T2#
T2OE
WTO0
CP/RL2#
DCEN
7
TF1
GATE1
6
TR1
C/T1#
5
TF0
M11
4
TR0
M01
3
IE1
GATE0
2
IT1
C/T0#
1
IE0
M10
0
IT0
M00
RCAP2L
TH2
CAh
CDh
5
4235K–8051–05/08
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