Features
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4-Kbyte ROM, 256
×
4-bit RAM
16 Bidirectional I/Os
Up to 7 External/Internal Interrupt Sources
Multifunction Timer/Counter with
IR Remote Control Carrier Generator
Bi-phase-, Manchester- and Pulse-width Modulator and Demodulator
Phase Control Function
Programmable System Clock with Prescaler and Five Different Clock Sources
Wide Supply-voltage Range (1.8V to 6.5V)
Very Low Sleep Current (< 1 µA)
32
×
16-bit EEPROM (ATAR092 only)
Synchronous Serial Interface (2-wire, 3-wire)
Watchdog, POR and Brown-out Function
Voltage Monitoring Inclusive Lo_BAT Detect
Flash Controller ATAM893 Available (SSO20)
Low-current
Microcontroller
for Wireless
Communication
ATAR092
ATAR892
1. Description
The ATAR092 and ATAR892 are members of Atmel ’s family of 4-bit single-chip
microcontrollers. They offer highest integration for IR and RF data communication,
remote-control and phase-control applications. The ATAR092 and ATAR892 are suit-
able for the transmitter side as well as the receiver side. They contain ROM, RAM,
parallel I/O ports, two 8-bit programmable multifunction timer/counters with modulator
and demodulator function, voltage supervisor, interval timer with watchdog function
and a sophisticated on-chip clock generation with external clock input, integrated RC-,
32-kHz crystal- and 4-MHz crystal-oscillators. The ATAR892 has an additional
EEPROM as a second chip in one package.
Figure 1-1.
Block Diagram
V
SS
V
DD
OSC1 OSC2
®
Brown-out Protect
RESET
Voltage Monitor
External Input
VMI
BP10
Port 1
BP13
RC
Crystal
Oscillators Oscillators
External
Clock Input
UTCM
Timer 1
Interval- and
Watchdog Timer
Timer 2
8/12-bit Timer
with Modulator
SSI
Serial Interface
Clock Management
T2I
T2O
SD
SC
T3O
T3I
ROM
4 K x 8 bit
RAM
256 x 4 bit
Data Direction
BP20/NTE
MARC4
4-bit CPU Core
I/O Bus
BP22
BP23
Port 2
BP21
Timer 3
8-bit
Timer/Counter
with Modulator
and Demodulator
Data Direction +
Alternate Function
Port 4
Data Direction +
Interrupt Control
Port 5
Data Direction +
Alternate Function
Port 6
BP42
BP40
INT3
T2O
SC
BP41
BP43
VMI
INT3
T2I
SD
BP50
INT6
BP52
INT1
BP53
INT1
BP60
T3O
BP63
T31
BP51
INT6
4535E–4BMCU–05/07
2. Pin Configuration
Figure 2-1.
Pinning SSO20
VDD
BP40/INT3/SC
BP53/INT1
BP52/INT1
BP51/INT6
BP50/INT6
OSC1
OSC2
BP60/T3O
BP10
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VSS
BP43/INT3/SD
BP42/T2O
BP41/VMI/T2I
BP23
BP22
BP21
BP20/NTE
BP63/T3I
BP13
Table 2-1.
Name
VDD
VSS
BP10
BP13
BP20
BP21
BP22
BP23
BP40
BP41
BP42
BP43
BP50
BP51
BP52
BP53
BP60
BP63
OSC1
Pin Description
Type
–
–
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Function
Supply voltage
Circuit ground
Bidirectional I/O line of Port 1.0
Bidirectional I/O line of Port 1.3
Bidirectional I/O line of Port 2.0
Bidirectional I/O line of Port 2.1
Bidirectional I/O line of Port 2.2
Bidirectional I/O line of Port 2.3
Bidirectional I/O line of Port 4.0
Bidirectional I/O line of Port 4.1
Bidirectional I/O line of Port 4.2
Bidirectional I/O line of Port 4.3
Bidirectional I/O line of Port 5.0
Bidirectional I/O line of Port 5.1
Bidirectional I/O line of Port 5.2
Bidirectional I/O line of Port 5.3
Bidirectional I/O line of Port 6.0
Bidirectional I/O line of Port 6.3
Oscillator input
Alternate Function
–
–
–
–
NTE-test mode enable, see section “Master Reset”
–
–
–
SC-serial clock or INT3 external interrupt input
VMI voltage monitor input or T2I external clock
input Timer 2
T2O Timer 2 output
SD serial data I/O or INT3-external interrupt input
INT6 external interrupt input
INT6 external interrupt input
INT1 external interrupt input
INT1 external interrupt input
T3O Timer 3 output
T3I Timer 3 input
4-MHz crystal input or 32-kHz crystal input or
external clock input or external trimming resistor
input
4-MHz crystal output or 32-kHz crystal output or
external clock input
Pin No.
1
20
10
11
13
14
15
16
2
17
18
19
6
5
4
3
9
12
7
Reset State
NA
NA
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
OSC2
O
Oscillator output
8
NA
2
ATAR092/ATAR892
4535E–4BMCU–05/07
ATAR092/ATAR892
3. Introduction
The ATAR092/ATAR892 are members of Atmel’s family of 4-bit single-chip microcontrollers.
They contain ROM, RAM, parallel I/O ports, two 8-bit programmable multi-function
timer/counters, voltage supervisor, interval timer with watchdog function and a sophisticated
on-chip clock generation with integrated RC-, 32-kHz crystal- and 4-MHz crystal oscillators.
Table 3-1.
Version
Flash device
Production
Production
Available Variants of ATAxx9x
Type
ATAM893
ATAR092
ATAR892
ROM
4-Kbyte EEPROM
4-Kbyte mask ROM
4-Kbyte mask ROM
E2PROM Peripheral
64 byte
–
64 byte
Packages
SSO20
SSO20
SSO20
4. MARC4 Architecture
4.1
General Description
The MARC4 microcontroller consists of an advanced stack-based, 4-bit CPU core and on-chip
peripherals. The CPU is based on the HARVARD architecture with physically separate program
memory (ROM) and data memory (RAM). Three independent buses, the instruction bus, the
memory bus and the I/O bus, are used for parallel communication between ROM, RAM and
peripherals. This enhances program execution speed by allowing both instruction prefetching,
and a simultaneous communication to the on-chip peripheral circuitry. The extremely powerful
integrated interrupt controller with associated eight prioritized interrupt levels supports fast and
efficient processing of hardware events. The MARC4 is designed for the high-level programming
language qFORTH. The core includes both an expression and a return stack. This architecture
enables high-level language programming without any loss of efficiency or code density.
Figure 4-1.
MARC4 Core
MARC4 CORE
Reset
Program
Memory
PC
X
Y
SP
RP
RAM
256 x 4-bit
Reset
Clock
Instruction
Bus
Instruction
Decoder
Memory Bus
TOS
CCR
System
Clock
Sleep
Interrupt
Controller
I/O Bus
ALU
On-chip Peripheral Modules
3
4535E–4BMCU–05/07
4.2
Components of MARC4 Core
The core contains ROM, RAM, ALU, program counter, RAM address registers, instruction
decoder and interrupt controller. The following sections describe each functional block in more
detail.
4.2.1
ROM
The program memory (ROM) is mask programmed with the customer application program dur-
ing the fabrication of the microcontroller. The 4 Kbyte ROM size is addressed by a 12-bit wide
program counter. An additional 1 Kbyte of ROM exists which is reserved for quality control
self-test software The lowest user ROM address segment is taken up by a 512-byte zero page
which contains predefined start addresses for interrupt service routines and special subroutines
accessible with single byte instructions (SCALL).
The corresponding memory map is shown in
Figure 4-2
Look-up tables of constants can also be
held in ROM and are accessed via the MARC4’s built-in table instruction.
Figure 4-2.
ROM Map
FFFh
1F8h
1F0h
1E8h
1E0h
1E0h
1C0h
180h
INT7
INT6
INT5
INT4
INT3
INT2
INT1
INT0
ROM
SCALL Addresses
(4 K x 8 Bit)
7FFh
Zero
page
140h
100h
0C0h
080h
040h
1FFh
Zero Page
000h
020h
018h
010h
008h
000h
008h
000h
$RESET
$AUTOSLEEP
4.2.2
RAM
The ATAR092 and ATAR892 contain 256 x 4-bit wide static random access memory (RAM). It is
used for the expression stack, the return stack and data memory for variables and arrays. The
RAM is addressed by any of the four 8-bit wide RAM address registers SP, RP, X and Y.
4.2.2.1
Expression Stack
The 4-bit wide expression stack is addressed with the expression stack pointer (SP). All arith-
metic, I/O and memory reference operations take their operands from, and return their results to
the expression stack. The MARC4 performs the operations with the top of stack items (TOS and
TOS-1). The TOS register contains the top element of the expression stack and works in the
same way as an accumulator. This stack is also used for passing parameters between subrou-
tines and as a scratch pad area for temporary storage of data.
4
ATAR092/ATAR892
4535E–4BMCU–05/07
ATAR092/ATAR892
4.2.2.2
Return Stack
The 12-bit wide return stack is addressed by the return stack pointer (RP). It is used for storing
return addresses of subroutines, interrupt routines and for keeping loop index counts. The return
stack can also be used as a temporary storage area.
The MARC4 instruction set supports the exchange of data between the top elements of the
expression stack and the return stack. The two stacks within the RAM have a user definable
location and maximum depth.
Figure 4-3.
RAM Map
RAM
(256 x 4-bit)
Autosleep
Expression Stack
3
0
SP
FCh
FFh
Global
Variables
TOS
TOS-1
TOS-2
RAM Address Register
X
Y
4-bit
SP
TOS-1
Expression
Stack
Return
Stack
Global
Variables
07h
03h
Return Stack
11
0
RP
RP
04h
00h
12-bit
4.2.3
Registers
The MARC4 controller has seven programmable registers and one condition code register. They
are shown in the following programming model.
4.2.3.1
Program Counter (PC)
The program counter is a 12-bit register which contains the address of the next instruction to be
fetched from the ROM. Instructions currently being executed are decoded in the instruction
decoder to determine the internal micro-operations. For linear code (no calls or branches) the
program counter is incremented with every instruction cycle. If a branch-, call-, return-instruction
or an interrupt is executed, the program counter is loaded with a new address. The program
counter is also used with the table instruction to fetch 8-bit wide ROM constants.
5
4535E–4BMCU–05/07
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