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EPM7256BTC144-5

Description
EE PLD, 5ns, 256-Cell, CMOS, PQFP144, TQFP-144
CategoryProgrammable logic devices    Programmable logic   
File Size1MB,76 Pages
ManufacturerIntel
Websitehttp://www.intel.com/
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EPM7256BTC144-5 Overview

EE PLD, 5ns, 256-Cell, CMOS, PQFP144, TQFP-144

EPM7256BTC144-5 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
package instructionLFQFP, QFP144,.63SQ,20
Reach Compliance Codecompliant
ECCN code3A991
Other featuresYES
maximum clock frequency188.7 MHz
In-system programmableYES
JESD-30 codeS-PQFP-G144
JESD-609 codee0
JTAG BSTYES
length20 mm
Humidity sensitivity level3
Dedicated input times
Number of I/O lines120
Number of macro cells256
Number of terminals144
Maximum operating temperature70 °C
Minimum operating temperature
organize0 DEDICATED INPUTS, 120 I/O
Output functionMACROCELL
Package body materialPLASTIC/EPOXY
encapsulated codeLFQFP
Encapsulate equivalent codeQFP144,.63SQ,20
Package shapeSQUARE
Package formFLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)220
power supply1.8/3.3,2.5 V
Programmable logic typeEE PLD
propagation delay5 ns
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum supply voltage2.625 V
Minimum supply voltage2.375 V
Nominal supply voltage2.5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width20 mm
Base Number Matches1
MAX 7000B
®
Programmable Logic
Device
Data Sheet
September 2005, ver. 3.5
Features...
High-performance 2.5-V CMOS EEPROM-based programmable logic
devices (PLDs) built on second-generation Multiple Array MatriX
(MAX
®
) architecture (see
Table 1)
Pin-compatible with the popular 5.0-V MAX 7000S and 3.3-V
MAX 7000A device families
High-density PLDs ranging from 600 to 10,000 usable gates
3.5-ns pin-to-pin logic delays with counter frequencies in excess
of 303.0 MHz
Advanced 2.5-V in-system programmability (ISP)
Programs through the built-in IEEE Std. 1149.1 Joint Test Action
Group (JTAG) interface with advanced pin-locking capability
– Enhanced ISP algorithm for faster programming
ISP_Done bit to ensure complete programming
Pull-up resistor on I/O pins during in-system programming
ISP circuitry compliant with IEEE Std. 1532
f
For information on in-system programmable 5.0-V MAX 7000S or 3.3-V
MAX 7000A devices, see the
MAX 7000 Programmable Logic Device Family
Data Sheet
or the
MAX 7000A Programmable Logic Device Family Data Sheet.
Table 1. MAX 7000B Device Features
Feature
Usable gates
Macrocells
Logic array blocks
Maximum user I/O
pins
t
PD
(ns)
t
SU
(ns)
t
FSU
(ns)
t
CO1
(ns)
f
CNT
(MHz)
EPM7032B
600
32
2
36
3.5
2.1
1.0
2.4
303.0
EPM7064B
1,250
64
4
68
3.5
2.1
1.0
2.4
303.0
EPM7128B
2,500
128
8
100
4.0
2.5
1.0
2.8
243.9
EPM7256B
5,000
256
16
164
5.0
3.3
1.0
3.3
188.7
EPM7512B
10,000
512
32
212
5.5
3.6
1.0
3.7
163.9
Altera Corporation
DS-MAX7000B-3.5
1
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