Low Capacitance TVS
for Ethernet and Telecom Interfaces
PROTECTION PRODUCTS - TransClamp
ΤΜ
Description
A TransClamp
ΤΜ
is a low capacitance TVS array designed
to protect high speed data interfaces. This series has
been specifically designed to protect sensitive compo-
nents which are connected to data and transmission
lines from overvoltage caused by
ESD
(electrostatic
discharge),
CDE
(Cable Discharge Events), and
Light-
ning.
These devices integrate low capacitance, surge-rated
compensation diodes with a high power transient
voltage suppressor (TVS). The compensation diodes
are arranged in a bridge pattern allowing the device to
be connected in common mode and/or differential
mode. This allows the designer maximum flexibility and
reduces parts count. The capacitance of the device is
limited to 12pF maximum from line-to-line to ensure
correct signal transmission on high-speed lines.
These devices may be used to meet Telcordia GR-1089-
CORE short-haul (intra-building) surge requirements and
will withstand a minimum 100 A surge for a 2/10μs
pulse.
The TClamp
TM
2502N is in a 10-pin, RoHS/WEEE
compliant, SLP2626P10 package. It measures 2.6 x
2.6 x 0.60mm. The leads are spaced at a pitch of
0.5mm and are finished with lead-free NiPdAu. They
are particularly well suited for applications where board
space is at a premium such as integrated connectors/
magnetics and carrier class Ethernet equipment.
TClamp2502N
Features
Transient protection for high-speed data lines to
Bellcore 1089 (Intra-Building) 100A (2/10μs)
IEC 61000-4-2 (ESD) ±15kV (air), ±8kV (contact)
IEC 61000-4-4 (EFT) 40A (5/50ns)
IEC 61000-4-5 (Lightning) L5, 95A (8/20μs)
Low capacitance (12pF line-to-line)
Low operating voltages
(2.5V)
Low clamping voltage
Small SLP Package saves board space
Solid-state technology
Mechanical Characteristics
SLP2626P10 10L package
RoHS/WEEE Compliant
Nominal Dimensions: 2.6 x 2.6 x 0.60 mm
Lead Pitch: 0.5mm
Molding compound flammability rating: UL 94V-0
Marking: Marking Code + Date Code
Packaging: Tape and Reel per EIA 481
Applications
Ethernet
T3/E3
Integrated Magnetics
Carrier Class Equipment
Customer Premise Equipment
Circuit Diagram
LINE 1
(1, 2, 3)
Package Configuration
2.60
1 2
C
L
C
2.60
L
Center Tab
0.50 BSC
LINE 2
(8, 9, 10)
0.60
10 Pin SLP package (Bottom Side View)
Nominal Dimensions in mm
Revision 04/04/2007
1
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TClamp2502N
PROTECTION PRODUCTS
Absolute Maximum Rating
Rating
Peak Pulse Power (tp = 2/10
μ
s)
Peak Pulse Current (tp = 2/10
μ
s)
Peak Pulse Current (tp = 8/20
μ
s)
ESD per IEC 61000-4-2 (Air)
ESD per IEC 61000-4-2 (Contact)
Operating Temperature
Storage Temperature
Symbol
P
pk
I
PP
I
PP
V
ESD
T
J
T
STG
Value
2500
120
95
30
30
-40 to +85
-55 to +150
Units
Watts
A
A
kV
°C
°C
Electrical Characteristics (T=25
o
C unless otherwise specified)
TClamp2502N
Parameter
Reverse Stand-Off Voltage
Punch-Through Voltage
Snap-Back Voltage
Reverse Leakage Current
Clamping Voltage
Clamping Voltage
Junction Capacitance
Symbol
V
RWM
V
PT
V
SB
I
R
V
C
V
C
C
j
Conditions
T=25°C to 85°C
I
PT
= 2
μ
A
T=25°C
I
SB
= 50mA
V
RWM
= 2.5V, T=25°C
I
PP
= 100A, tp = 2/10
μ
s
Line-to-Ground
I
PP
= 100A, tp = 2/10
μ
s
Line-to-Line
Between I/O pins and
Gnd
V
R
= 0V, f = 1MHz
Between I/O pins
V
R
= 0V, f = 1MHz
2.7
2.0
0.5
17
25
25
Minimum
Typical
Maximum
2.5
Units
V
V
V
μ
A
V
V
pF
12
pF
©
2007 Semtech Corp.
2
www.semtech.com
TClamp2502N
PROTECTION PRODUCTS
Applications Information
Device Connection Options for Protection of Two
High-Speed Data Lines
TClamp2502N is designed to protect two high-speed
data lines (one differential pair) from transient over-
voltages which result from lightning and ESD. They can
be configured to protect in differential (Line-to-Line)
and common (Line-to-Ground) mode. Data line inputs/
outputs are connected at pins 1, 2 and 3, and 8, 9
and 10 as shown. For proper operation, pins 1 - 3
must be connected together and pins 8 - 10 must be
connected together. Pins 4, 5, 6, and 7 may be left
unconnected. For differential operation, the center tab is
also left not connected. For common mode operation,
the center tab is connected to ground. The ground
connection should be made directly to a ground plane
on the board for best results. The use of multiple vias
is recommended for reduced ground loop inductance.
Circuit Diagram
LINE 1
(1, 2, 3)
Center Tab
LINE 2
(8, 9, 10)
Configuration (Top
View)
Pin Conf iguration (Top Side Vie w)
1
2
3
4
5
GND
10
9
8
7
6
Pin
1, 2, 3
8, 9, 10
4, 5, 6, 7
Center Tab
Identification
Line 1 in/out
Line 2 in/out
N o Connect
Ground
©
2007 Semtech Corp.
5
www.semtech.com
Embedded System
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