AT572D940HF datasheet, PDF - EEWORLD Datasheet

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AT572D940HF: DescriptionDIOPSIS 940HF ARM926EJ-S PLUS ONE GFLOPS DSP; CategoryThe embedded processor and controller Microcontrollers and processors; File Size4MB，745 Pages; ManufacturerAtmel (Microchip); Environmental Compliance

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AT572D940HF Overview

DIOPSIS 940HF ARM926EJ-S PLUS ONE GFLOPS DSP

AT572D940HF Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Parts packaging code	BGA
package instruction	LFBGA, BGA324,18X18,32
Contacts	324
Reach Compliance Code	compli
Is Samacsys	N
Address bus width	26
bit size	32
boundary scan	YES
maximum clock frequency	50 MHz
External data bus width	32
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	S-PBGA-B324
length	15 mm
low power mode	YES
Number of terminals	324
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	LFBGA
Encapsulate equivalent code	BGA324,18X18,32
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	1.1 V
Certification status	Not Qualified
RAM (number of words)	24576
Maximum seat height	1.5 mm
speed	160 MHz
Maximum supply voltage	1.15 V
Minimum supply voltage	1.05 V
Nominal supply voltage	1.1 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	15 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC
Base Number Matches	1

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Features

•

DIOPSIS

Dual Core System Integrating an ARM926EJ-S

™

ARM

Thumb

Processor

Core and a MagicV of VLIW Magic DSP

™

is optimized for Audio, Communication and

Beam-forming Applications

High Performance MagicV VLIW DSP

– 1 GFLOPS - 1.6 Gops at 100 MHz

– AHB Master Port, integrated DMA Engine and AHB Slave Port

– Up to 10 Arithmetic Operations per Cycle (4 Multiply, 2 Add/Subtract, 1 Add, 1

Subtract 40-bit Floating Point and 32-bit Integer) allowing Single Cycle FFT

Butterfly

– Native Support for Complex Arithmetic and Vectorial SIMD Operations: One

Complex Multiply with Dual Add/Sub per Clock Cycle or Two Multiply and Two

Add/sub or Simple Scalar Operations

– 32-bit Integer and IEEE

40-bit Extended Precision Floating Point Numeric Format

– 16-port Data Register File: 256 Registers organized in Two 128-register Banks

– 5-issue predicated VLIW Architecture with Orthogonal ISA, Code Compression

and Hardware Support for Code Efficient Software Pipeline Loops

– 6 Accesses per Cycle Data Memory System (4 Accesses per Cycle for VLIW

Operations + 2 Accesses per Cycle for DMA Transfers) supported by Flexible

Addressing Capability

– 2 Independent Address Generation Units Operating on a 64-register Address

Programmable Stride and Circular Buffers

– 1.7 Mbits of On-chip SRAM:

– 16 K x 40-bit Data Memory Locations (6 Memory Accesses per Cycle)

– 8 K x 128-bit Dual Port Program Memory Location, Equivalent to ~50K DSP

Assembler Instructions (typical) thanks to Code Compression and SW Pipelining

– DMA Access to the External Program and Data Memory

– Three Main Operating Modes: Run, Debug and Sleep

– User Mode and Privileged Interrupt Service Mode

– Efficient Optimizing Assembler and C-Oriented Architecture: allows Easy

Exploitation of the available Hardware Parallelism

– ARM926EJ-S ARM Thumb Processor

– DSP Instruction Extensions

– ARM Jazelle

Technology for Java

Acceleration

– 16-KByte Data Cache, 16-KByte Instruction Cache, Write Buffer

– 220MIPS at 200MHz

– Memory Management Unit

– EmbeddedICE

™

In-circuit Emulation, Debug Communication Channel Support

Additional Embedded Memories

– 32-KByte of internal ROM, two-cycle access at maximum bus speed

– 48-KByte of internal SRAM, single-cycle access at maximum processor or bus

speed

External Bus Interface (EBI)

– Supports SDRAM, Static Memory, SmartMedia

™

and NAND Flash, CompactFlash

™

USB

– USB 2.0 Full Speed (12 Mbits per second) Host Double Port

– Dual On-chip Transceivers

– Integrated FIFOs and Dedicated DMA Channels

•

DIOPSIS 940HF

ARM926EJ-S PLUS

ONE GFLOPS DSP

AT572D940HF

Preliminary

•

7010A–DSP–07/08

1. Description

DIOPSIS 940HF is a Dual CPU Processor integrating a MagicV VLIW DSP and an ARM926EJ-

S RISC MCU, plus a 370 Kbyte SRAM. The system combines the flexibility of the ARM926

RISC controller with the very high performance of the DSP.

MagicV is a high performance VLIW DSP delivering 1 Giga floating-point operations per second

(GFLOPS) and 1.6 Gops at 100 MHz clock rate. It is equipped with an AHB master port and an

AHB slave port for system-on-chip integration. It has 256 data registers, 64 address registers, 10

independent arithmetic operating units, 2 independent address generation units and a DMA

engine. To sustain the internal parallelism, the data bandwidth among the Register File, the

Operators and the Data Memory System, is 80 bytes/cycle. The Data Memory System is

designed to transfer 28 bytes/cycle. For instance, MagicV can produce a complete FFT butterfly

per cycle by activating all the computing units; it operates on IEEE 754 40-bit extended precision

floating-point and 32-bit integer numeric format for numerical computations, while internal mem-

ory accesses are supported by a powerful 16-bit MAGU (Multiple Address Generation Unit). It

has also on-chip 16K x 40-bit 6-access/cycle data memory system and 8K x 128-bit dual port

program memory locations. Efficient usage of the internal program memory is achieved through

a general purpose code compression mechanism and a software pipelining support for system-

atic loops.

A C-oriented Architecture and an optimizing assembler facilitate the user in dealing with the par-

allelism of the processor resources and drastically simplify the code development. A rich library

of C-callable DSP routines is available.

The ARM926 embedded micro controller core is a member of the Advanced RISC Machines

(ARM) family of general purpose 32-bit microprocessors, which offer high performance and very

low power consumption. The ARM architecture is based on Reduced Instruction Set Computer

(RISC) principles; the instruction set and the related decode mechanism are much simpler than

the micro programmed Complex Instruction Set Computers.

The result of this simplicity is a high instruction throughput and an impressive real-time interrupt

response. The ARM926 supports 16-bit Thumb subset of the most commonly used 32-bit

instructions. These are expanded at run time with no degradation of the system performance.

This gives 16-bit code density (saving memory area and cost) coupled with a 32-bit processor

performance.

A rich set of peripherals and a 48 Kbyte internal memory provide a highly flexible and integrated

system solution.

The ARM926EJ-S supports Jazelle Technology for Java acceleration.

AT572D940HF Preliminary

7010A–DSP–07/08

AT572D940HF Related Products

	AT572D940HF	AT572D940HF-CJ	AT572D940HF_08	AT572D940HF-CL
Description	DIOPSIS 940HF ARM926EJ-S PLUS ONE GFLOPS DSP	DIOPSIS 940HF ARM926EJ-S PLUS ONE GFLOPS DSP	DIOPSIS 940HF ARM926EJ-S PLUS ONE GFLOPS DSP	DIOPSIS 940HF ARM926EJ-S PLUS ONE GFLOPS DSP
Is it Rohs certified?	conform to	conform to	-	conform to
Parts packaging code	BGA	BGA	-	BGA
package instruction	LFBGA, BGA324,18X18,32	LFBGA, BGA324,18X18,32	-	LFBGA, BGA324,18X18,32
Contacts	324	324	-	324
Reach Compliance Code	compli	compli	-	compli
Address bus width	26	26	-	26
bit size	32	32	-	32
boundary scan	YES	YES	-	YES
maximum clock frequency	50 MHz	50 MHz	-	50 MHz
External data bus width	32	32	-	32
Format	FLOATING POINT	FLOATING POINT	-	FLOATING POINT
Integrated cache	YES	YES	-	YES
JESD-30 code	S-PBGA-B324	S-PBGA-B324	-	S-PBGA-B324
length	15 mm	15 mm	-	15 mm
low power mode	YES	YES	-	YES
Number of terminals	324	324	-	324
Maximum operating temperature	70 °C	85 °C	-	70 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	-	PLASTIC/EPOXY
encapsulated code	LFBGA	LFBGA	-	LFBGA
Encapsulate equivalent code	BGA324,18X18,32	BGA324,18X18,32	-	BGA324,18X18,32
Package shape	SQUARE	SQUARE	-	SQUARE
Package form	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	-	GRID ARRAY, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	-	NOT SPECIFIED
power supply	1.1 V	1.2 V	-	1.2 V
Certification status	Not Qualified	Not Qualified	-	Not Qualified
RAM (number of words)	24576	24576	-	24576
Maximum seat height	1.5 mm	1.5 mm	-	1.5 mm
speed	160 MHz	200 MHz	-	160 MHz
Maximum supply voltage	1.15 V	1.26 V	-	1.26 V
Minimum supply voltage	1.05 V	1.14 V	-	1.14 V
Nominal supply voltage	1.1 V	1.2 V	-	1.2 V
surface mount	YES	YES	-	YES
technology	CMOS	CMOS	-	CMOS
Temperature level	COMMERCIAL	INDUSTRIAL	-	COMMERCIAL
Terminal form	BALL	BALL	-	BALL
Terminal pitch	0.8 mm	0.8 mm	-	0.8 mm
Terminal location	BOTTOM	BOTTOM	-	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	-	NOT SPECIFIED
width	15 mm	15 mm	-	15 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	-	MICROPROCESSOR, RISC

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