Features
•
DIOPSIS
®
Dual Core System Integrating an ARM926EJ-S
™
ARM
®
Thumb
®
Processor
Core and a MagicV of VLIW Magic DSP
™
is optimized for Audio, Communication and
Beam-forming Applications
High Performance MagicV VLIW DSP
– 1 GFLOPS - 1.6 Gops at 100 MHz
– AHB Master Port, integrated DMA Engine and AHB Slave Port
– Up to 10 Arithmetic Operations per Cycle (4 Multiply, 2 Add/Subtract, 1 Add, 1
Subtract 40-bit Floating Point and 32-bit Integer) allowing Single Cycle FFT
Butterfly
– Native Support for Complex Arithmetic and Vectorial SIMD Operations: One
Complex Multiply with Dual Add/Sub per Clock Cycle or Two Multiply and Two
Add/sub or Simple Scalar Operations
– 32-bit Integer and IEEE
®
40-bit Extended Precision Floating Point Numeric Format
– 16-port Data Register File: 256 Registers organized in Two 128-register Banks
– 5-issue predicated VLIW Architecture with Orthogonal ISA, Code Compression
and Hardware Support for Code Efficient Software Pipeline Loops
– 6 Accesses per Cycle Data Memory System (4 Accesses per Cycle for VLIW
Operations + 2 Accesses per Cycle for DMA Transfers) supported by Flexible
Addressing Capability
– 2 Independent Address Generation Units Operating on a 64-register Address
Register File Supporting Complex or Micro-Vectorial Accesses and DSP features:
Programmable Stride and Circular Buffers
– 1.7 Mbits of On-chip SRAM:
– 16 K x 40-bit Data Memory Locations (6 Memory Accesses per Cycle)
– 8 K x 128-bit Dual Port Program Memory Location, Equivalent to ~50K DSP
Assembler Instructions (typical) thanks to Code Compression and SW Pipelining
– DMA Access to the External Program and Data Memory
– Three Main Operating Modes: Run, Debug and Sleep
– User Mode and Privileged Interrupt Service Mode
– Efficient Optimizing Assembler and C-Oriented Architecture: allows Easy
Exploitation of the available Hardware Parallelism
– ARM926EJ-S ARM Thumb Processor
– DSP Instruction Extensions
– ARM Jazelle
®
Technology for Java
®
Acceleration
– 16-KByte Data Cache, 16-KByte Instruction Cache, Write Buffer
– 220MIPS at 200MHz
– Memory Management Unit
– EmbeddedICE
™
In-circuit Emulation, Debug Communication Channel Support
Additional Embedded Memories
– 32-KByte of internal ROM, two-cycle access at maximum bus speed
– 48-KByte of internal SRAM, single-cycle access at maximum processor or bus
speed
External Bus Interface (EBI)
– Supports SDRAM, Static Memory, SmartMedia
™
and NAND Flash, CompactFlash
™
USB
– USB 2.0 Full Speed (12 Mbits per second) Host Double Port
– Dual On-chip Transceivers
– Integrated FIFOs and Dedicated DMA Channels
•
DIOPSIS 940HF
ARM926EJ-S PLUS
ONE GFLOPS DSP
AT572D940HF
Preliminary
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7010A–DSP–07/08
•
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– USB 2.0 Full Speed (12 Mbits per second) Device Port
– On-chip Transceiver, 2-Kbyte Configurable Integrated FIFOs
– Two dedicated PDC channels
Ethernet MAC 10/100
– Reduced Media Independent Interface (RMII) to Physical Layer
– Integrated DMA channel
AHB bus Matrix
– Seven Masters and Five Slaves Handled
– Boot Mode Select Option
– Remap Command
System Controller (SYSC)
– Reset Controller
– Periodic Interval Timer,
Watchdog and Real-Time Timer
Power Management Controller (PMC)
– Very Slow Clock (32768Hz) Operating Mode
– Software Programmable Power Optimization Capabilities
– 3 to 20 MHz On-chip Oscillator and two PLLs
– Four Programmable External Clock Signals
Advanced Interrupt Controller (AIC)
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
– Three External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected
Three 32-bit Parallel Input/Output Controllers (PIO)
– 96 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os
– Input Change Interrupt Capability on Each I/O Line
– Individually Programmable Open-drain, Pull-up resistor and Synchronous Output
Twenty-three Peripheral Data Controller (PDC) Channels
Debug Unit (DBGU)
– 2-wire USART and support for Debug Communication Channel, Programmable ICE Access Prevention
– Two dedicated PDC channels
Four
Synchronous Serial Controllers (SSC)
– Two Independent Clock and Frame Sync Pair Signals for Each Receiver and Transmitter
– I²S Analog Interface Support, Time Division Multiplex Support
– High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
– Two dedicated PDC channels for each SSC
Three Universal Synchronous/Asynchronous Receiver Transmitters (USART)
– Individual Baud Rate Generator, IrDA
®
Infrared Modulation/Demodulation
– Support for ISO7816 T0/T1 Smart Card, Hardware and Software Handshaking, RS485 Support
– Two dedicated PDC channels for each USART
Two Master/Slave Serial Peripheral Interface (SPI)
– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
– Two dedicated PDC Channels for each SPI
One Three-channel 16-bit Timer/Counters (TC)
– Three External Clock Inputs, Two multi-purpose I/O Pins per Channel
– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
Two Two-wire Interfaces (TWI)
– Master Mode Support, All Atmel Two-wire EEPROMs Supported
Two CAN Interfaces
– Fully compliant with CAN 2.0 Part A and 2.0 Part B
Multimedia Card Interface (MCI)
– Automatic Protocol Control and Fast Automatic Data Transfers with PDMA, MMC and SDCard Compliant
2
AT572D940HF Preliminary
7010A–DSP–07/08
AT572D940HF Preliminary
•
IEEE 1149.1 JTAG Boundary Scan on All Digital Pins
•
Required Power Supplies:
– 1.1V / 1.2V for VDDCORE and VDDOSC
– 3.3V for VDDPLLA
– 3.3V for VDDIOP (Peripheral I/Os) and for VDDIOM (Memory I/Os)
•
Available in 324-ball CABGA Package
•
Efficient ARM - DSP Interface through AHB master and slave ports, Memory Mapped Registers and Ports, Interrupt Lines and
Semaphores
3
7010A–DSP–07/08
1. Description
DIOPSIS 940HF is a Dual CPU Processor integrating a MagicV VLIW DSP and an ARM926EJ-
S RISC MCU, plus a 370 Kbyte SRAM. The system combines the flexibility of the ARM926
TM
RISC controller with the very high performance of the DSP.
MagicV is a high performance VLIW DSP delivering 1 Giga floating-point operations per second
(GFLOPS) and 1.6 Gops at 100 MHz clock rate. It is equipped with an AHB master port and an
AHB slave port for system-on-chip integration. It has 256 data registers, 64 address registers, 10
independent arithmetic operating units, 2 independent address generation units and a DMA
engine. To sustain the internal parallelism, the data bandwidth among the Register File, the
Operators and the Data Memory System, is 80 bytes/cycle. The Data Memory System is
designed to transfer 28 bytes/cycle. For instance, MagicV can produce a complete FFT butterfly
per cycle by activating all the computing units; it operates on IEEE 754 40-bit extended precision
floating-point and 32-bit integer numeric format for numerical computations, while internal mem-
ory accesses are supported by a powerful 16-bit MAGU (Multiple Address Generation Unit). It
has also on-chip 16K x 40-bit 6-access/cycle data memory system and 8K x 128-bit dual port
program memory locations. Efficient usage of the internal program memory is achieved through
a general purpose code compression mechanism and a software pipelining support for system-
atic loops.
A C-oriented Architecture and an optimizing assembler facilitate the user in dealing with the par-
allelism of the processor resources and drastically simplify the code development. A rich library
of C-callable DSP routines is available.
The ARM926 embedded micro controller core is a member of the Advanced RISC Machines
(ARM) family of general purpose 32-bit microprocessors, which offer high performance and very
low power consumption. The ARM architecture is based on Reduced Instruction Set Computer
(RISC) principles; the instruction set and the related decode mechanism are much simpler than
the micro programmed Complex Instruction Set Computers.
The result of this simplicity is a high instruction throughput and an impressive real-time interrupt
response. The ARM926 supports 16-bit Thumb subset of the most commonly used 32-bit
instructions. These are expanded at run time with no degradation of the system performance.
This gives 16-bit code density (saving memory area and cost) coupled with a 32-bit processor
performance.
A rich set of peripherals and a 48 Kbyte internal memory provide a highly flexible and integrated
system solution.
The ARM926EJ-S supports Jazelle Technology for Java acceleration.
4
AT572D940HF Preliminary
7010A–DSP–07/08
AT572D940HF Preliminary
2. Ball Configuration
Table 2-1.
Name
A0/NBS0
A1/NBS2/NWR2
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16/SD_BA0
A17/SD_BA1
A18
A19
A20
A21
A_JCFG
A_RTCK
A_TCK
A_TDI
A_TDO
A_TMS
A_NTRST
D0
D1
D2
D3
D4
AT572D940HF Ball Assignment (I/O: 191 balls)
Pin
B2
C2
C1
D4
D3
D1
E4
E3
F6
G6
F3
H8
F2
F1
G3
H7
G1
G2
H6
H3
J8
H2
N16
M17
N17
M14
M16
N15
M13
H1
J7
J2
J1
K9
Name
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
M_NTRST
M_TCK
M_TDI
M_TDO
M_TMS
NCS0
NCS1/SD_CS
Pin
K7
K5
K1
K2
K6
K8
L5
L1
L2
L4
L7
M3
L8
M4
M5
M6
N1
M7
N4
N5
P1
P3
P4
P5
R1
R2
R3
E16
F13
E15
E14
E17
F7
A6
Name
NCS2
NCS3/SM_NCS
NRD/NOE/CF_NOE
NRST
NWR0/NWE/CF_NWE
NWR1/NBS1/CF_NIOR
NWR3/NBS3/CF_NIOW
Pin
B7
E7
B6
J17
C6
D6
G7
F11
C11
A11
B11
H10
G10
D10
B17
A17
B16
A16
C15
H17
V15
U15
V16
T15
V17
T16
T17
U18
T18
R15
R18
H16
B9
D9
Name
PIOA27
PIOA28
PIOA29
PIOA30
PIOA31
PIOB0
PIOB1
PIOB2
PIOB3
PIOB4
PIOB5
PIOB6
PIOB7
PIOB8
PIOB9
PIOB10
PIOB11
PIOB12
PIOB13
PIOB14
PIOB15
PIOB16
PIOB17
PIOB18
PIOB19
PIOB20
PIOB21
PIOB22
PIOB23
PIOB24
PIOB25
PIOB26
PIOB27
PIOB28
Pin
G9
J9
A8
D8
B8
U8
L9
P9
R9
V9
L10
N10
V10
T10
P10
M10
N11
M11
L11
U12
T12
R12
N12
V13
U13
T13
P13
V14
R14
J10
H15
B12
A12
F9
PIOA0
PIOA1
PIOA2
PIOA3
PIOA4
PIOA5
PIOA6
PIOA7
PIOA8
PIOA9
PIOA10
PIOA11
PIOA12
PIOA13
PIOA14
PIOA15
PIOA16
PIOA17
PIOA18
PIOA19
PIOA20
PIOA21
PIOA22
PIOA23
PIOA24
PIOA25
PIOA26
5
7010A–DSP–07/08
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