xr
AUGUST 2005
ST16C654/654D
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.2
GENERAL DESCRIPTION
The ST16C654/654D
1
(654) is an enhanced quad
Universal Asynchronous Receiver and Transmitter
(UART) each with 64 bytes of transmit and receive
FIFOs, transmit and receive FIFO trigger levels,
automatic hardware and software flow control, and
data rates of up to 1.5 Mbps. Each UART has a set
of registers that provide the user with operating status
and control, receiver error indications, and modem
serial interface controls. Selectable interrupt polarity
provides flexibility to meet design requirements. An
internal loopback capability allows onboard
diagnostics. The 654 is available in 64 pin LQFP, 68
pin PLCC and 100 pin QFP packages. The 64 pin
package only offers the 16 mode interface, but the 68
and 100 pin packages offer an additional 68 mode
interface which allows easy integration with Motorola
processors. The ST16C654CQ64 (64 pin) offers
three
state
interrupt
output
while
the
ST16C654DCQ64 provides continuous interrupt
output. The 100 pin package provides additional
FIFO status outputs (TXRDY# and RXRDY# A-D),
separate infrared transmit data outputs (IRTX A-D)
and channel C external clock input (CHCCLK). The
ST16C654/654D is compatible with the industry
standard ST16C454 and ST16C654/554D.
N
OTE
:
1 Covered by U.S. Patent #5,649,122.
FEATURES
•
Pin-to-pin compatible with ST16C454, ST16C554
and TI’s TL16C554AFN and TL16C754BFN
•
Intel or Motorola Data Bus Interface select
•
Four independent UART channels
■
■
■
■
■
■
■
■
■
■
Register Set Compatible to 16C550
Data rates of up to 1.5 Mbps
64 Byte Transmit FIFO
64 Byte Receive FIFO with error tags
4 Selectable TX and RX FIFO Trigger Levels
Automatic Hardware (RTS/CTS) Flow Control
Automatic Software (Xon/Xoff) Flow Control
Progammable Xon/Xoff characters
Wireless Infrared (IrDA 1.0) Encoder/Decoder
Full modem interface
•
2.97V to 5.5V supply operation
•
Sleep Mode (200 uA typical)
•
Crystal oscillator or external clock input
APPLICATIONS
•
Portable Appliances
•
Telecommunication Network Routers
•
Ethernet Network Routers
•
Cellular Data Devices
•
Factory Automation and Process Controls
F
IGURE
1. ST16C654 B
LOCK
D
IAGRAM
2.97V to 5.5V VCC
GND
UART Channel A
64 Byte TX FIFO
UART
Regs
BRG
IR
TX & RX
ENDEC
64 Byte RX FIFO
TXB, RXB, IRTXB, DTRB#,
DSRB#, RTSB#, CTSB#,
CDB#, RIB#
TXC, RXC, IRTXC, DTRC#,
DSRC#, RTSC#, CTSC#,
CDC#, RIC#
TXD, RXD, IRTXD, DTRD#,
DSRD#, RTSD#, CTSD#,
CDD#, RID#
XTAL1
XTAL2
A2:A0
D7:D0
IOR#
IOW#
CSA#
CSB#
CSC#
CSD#
INTA
INTB
INTC
INTD
CHCCLK
TXRDY# A-D
RXRDY# A-D
Reset
16/68#
INTSEL
CLKSEL
Data Bus
Interface
TXA, RXA, IRTXA, DTRA#,
DSRA#, RTSA#, CTSA#,
CDA#, RIA#
UART Channel B
(same as Channel A)
UART Channel C
(same as Channel A)
UART Channel D
(same as Channel A)
Crystal Osc/Buffer
654 BLK
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
RXRDYD#
RXRDYD#
RXRDYA#
TXRDYD#
TXRDYD#
RID#
RID#
INTSEL
INTSEL
RXA
CDA#
CDD#
CDD#
VCC
VCC
RXD
RXD
GND
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
RIA#
94
93
92
91
90
89
88
87
86
85
84
83
82
81
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
100
RXRDYA#
RXA
CDA#
GND
D7
RIA#
99
98
97
96
95
100
N.C.
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
N.C.
N.C.
N.C.
N.C.
N.C.
TXRDYC#
IRTXC
IRTXB
TXRDYB#
N.C.
N.C.
N.C.
N.C.
N.C.
DSRC#
DSRB#
23
24
25
26
27
28
29
30
CTSC#
CTSB#
22
DTRC#
DTRB#
21
VCC
GND
20
RTSC#
RTSB#
19
N.C.
INTB
18
A4
CSB#
17
TXC
TXB
16
N.C.
IOW#
15
TXD
TXA
14
N.C.
CSA#
13
N.C.
INTA
12
RTSD#
RTSA#
11
GND
VCC
10
DTRD#
DTRA#
9
CTSD#
CTSA#
8
DSRD#
DSRA#
7
IRTXD
IRTXA
6
FSRS#
TXRDYA#
5
N.C.
N.C.
4
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
N.C.
78
N.C.
3
N.C.
79
N.C.
2
N.C.
N.C.
N.C.
FSRS#
IRTXD
DSRD#
CTSD#
DTRD#
GND
RTSD#
INTD
CSD#
TXD
IOR#
TXC
CSC#
INTC
RTSC#
VCC
DTRC#
CTSC#
DSRC#
IRTXC
TXRDYC#
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
80
N.C.
1
N.C.
1
N.C.
2
N.C.
3
N.C.
4
TXRDYA#
5
IRTXA
6
DSRA#
7
CTSA#
8
DTRA#
9
VCC
10
RTSA#
11
IRQ#
12
CSA#
13
ST16C654/654D
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
TXA
14
R/W#
15
ST16C654
100-pin QFP
Intel Mode
Connect 16/68# pin to VCC
ST16C654
100-pin QFP
Motorola Mode
Connect 16/68# pin to GND
F
IGURE
2. P
IN
O
UT
A
SSIGNMENT
F
OR
100-
PIN
QFP P
ACKAGES
I
N
16
AND
68 M
ODE
2
37
38
39
40
41
42
43
44
45
46
47
48
49
50
31
32
33
34
35
36
37
A2
A1
A0
A2
RXB
RXC
GND
RIB#
CDC#
RIC#
CDB#
16/68#
XTAL1
XTAL2
RESET
CLKSEL
TXRDY#
RXRDY#
CHCCLK
RXRDYB#
RXRDYC#
TXB
16
A3
17
N.C.
18
RTSB#
19
GND
20
DTRB#
21
CTSB#
22
DSRB#
23
IRTXB
24
TXRDYB#
25
N.C.
26
N.C.
27
N.C.
28
N.C.
29
N.C.
30
xr
31
32
33
34
35
36
38
A1
39
A0
40
41
42
43
44
45
46
47
48
49
50
RXB
RXC
GND
CDC#
RIB#
RIC#
CLKSEL
CDB#
16/68#
XTAL1
XTAL2
RESET
TXRDY#
RXRDY#
CHCCLK
REV. 5.0.2
RXRDYB#
RXRDYC#
xr
REV. 5.0.2
ST16C654/654D
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
F
IGURE
3. P
IN
O
UT
A
SSIGNMENT
F
OR
PLCC P
ACKAGES
I
N
16
AND
68 M
ODE AND
LQFP P
ACKAGES
INTSEL
CDD#
CDD#
63
60
59
58
57
56
55
CDA#
CDA#
RID#
RID#
62
RIA#
RIA#
GND
GND
GND
RXD
RXA
RXA
RXD
63
VCC
VCC
64
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
67
68
67
66
65
64
63
62
63
68
66
D0
DSRA#
CTSA#
DTRA#
VCC
RTSA#
INTA
CSA#
TXA
IOW#
TXB
CSB#
INTB
RTSB#
GND
DTRB#
CTSB#
DSRB#
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
60
59
58
57
56
55
DSRD#
CTSD#
DTRD#
GND
RTSD#
INTD
CSD#
TXD
IOR#
TXC
CSC#
INTC
RTSC#
VCC
DTRC#
CTSC#
DSRC#
DSRA#
CTSA#
DTRA#
VCC
RTSA#
IRQ#
CS#
TXA
R/W#
TXB
A3
N.C.
RTSB#
GND
DTRB#
CTSB#
DSRB#
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
65
9
8
7
6
5
4
3
2
1
9
8
7
6
5
4
3
2
1
DSRD#
CTSD#
DTRD#
GND
RTSD#
N.C.
N.C.
TXD
N.C.
TXC
A4
N.C.
RTSC#
VCC
DTRC#
CTSC#
DSRC#
ST16C654
68-pin PLCC
Intel Mode
(16/68# pin connected to VCC)
54
53
52
51
50
49
48
47
46
45
44
ST16C654
68-pin PLCC
Motorola Mode
(16/68# pin connected to GND)
54
53
52
51
50
49
48
47
46
45
44
TXRDY#
RXRDY#
RXRDY#
TXRDY#
CLKSEL
CLKSEL
RESET
RESET
XTAL1
XTAL2
XTAL1
XTAL2
RIB#
CDC#
RIB#
16/68#
16/68#
CDA#
RIA#
64
60
56
54
52
62
61
59
57
55
51
58
50
DSRA#
CTSA#
DTRA#
VCC
RTSA#
INTA
CSA#
TXA
IOW#
TXB
CSB#
INTB
RTSB#
GND
DTRB#
CTSB#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
21
29
23
22
26
30
31
25
27
17
20
18
19
24
28
32
63
53
49
CDD#
RID#
GND
D6
D5
D4
D3
D0
VCC
D7
D1
RXD
RXA
D2
48
47
46
45
44
DSRD#
CTSD#
DTRD#
GND
RTSD#
INTD
CSD#
TXD
IOR#
TXC
CSC#
INTC
RTSC#
VCC
DTRC#
CTSC#
ST16C654
ST16C654D
64-pin TQFP
Intel Mode Only
43
42
41
40
39
38
37
36
35
34
33
CLKSEL
RIB#
RIC#
DSRB#
CDC#
CDB#
A0
RESET
ORDERING INFORMATION
O
PERATING
P
ART
N
UMBER
ST16C654CJ68
ST16C654IJ68
ST16C654CQ64
ST16C654IQ64
P
ACKAGE
68-Lead PLCC
T
EMPERATURE
R
ANGE
0°C to +70°C
D
EVICE
S
TATUS
Active
Active
Active
Active
O
PERATING
P
ART
N
UMBER
ST16C654DCQ64
ST16C654DIQ64
ST16C654CQ100
ST16C654IQ100
P
ACKAGE
64-Lead LQFP
64-Lead LQFP
100-Lead QFP
100-Lead QFP
T
EMPERATURE
R
ANGE
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
D
EVICE
S
TATUS
Active
Active
Active
Active
68-Lead PLCC -40°C to +85°C
64-Lead LQFP
0°C to +70°C
64-Lead LQFP -40°C to +85°C
3
DSRC#
XTAL1
A1
XTAL2
A2
GND
RXC
RXB
CDC#
CDB#
CDB#
RXB
RIC#
RXB
RIC#
GND
GND
RXC
RXC
A2
A1
A0
A2
A1
A0
ST16C654/654D
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
xr
REV. 5.0.2
PIN DESCRIPTIONS
Pin Description
N
AME
64-LQFP 68-PLCC 100-QFP
T
YPE
P
IN
#
P
IN
#
P
IN
#
D
ESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
IOR#
(VCC)
22
23
24
60
59
58
57
56
55
54
53
40
32
33
34
5
4
3
2
1
68
67
66
52
37
38
39
95
94
93
92
91
90
89
88
66
I
Address data lines [2:0]. These 3 address lines select one of the
internal registers in UART channel A-D during a data bus transac-
tion.
Data bus lines [7:0] (bidirectional).
I/O
I
When 16/68# pin is at logic 1, the Intel bus interface is selected and
this input becomes read strobe (active low). The falling edge insti-
gates an internal read cycle and retrieves the data byte from an
internal register pointed by the address lines [A2:A0], puts the data
byte on the data bus to allow the host processor to read it on the ris-
ing edge.
When 16/68# pin is at logic 0, the Motorola bus interface is selected
and this input is not used and should be connected to VCC.
When 16/68# pin is at logic 1, it selects Intel bus interface and this
input becomes write strobe (active low). The falling edge instigates
the internal write cycle and the rising edge transfers the data byte on
the data bus to an internal register pointed by the address lines.
When 16/68# pin is at logic 0, the Motorola bus interface is selected
and this input becomes read (logic 1) and write (logic 0) signal.
When 16/68# pin is at logic 1, this input is chip select A (active low)
to enable channel A in the device.
When 16/68# pin is at logic 0, this input becomes the chip select
(active low) for the Motorola bus interface.
When 16/68# pin is at logic 1, this input is chip select B (active low)
to enable channel B in the device.
When 16/68# pin is at logic 0, this input becomes address line A3
which is used for channel selection in the Motorola bus interface.
When 16/68# pin is at logic 1, this input is chip select C (active low)
to enable channel C in the device.
When 16/68# pin is at logic 0, this input becomes address line A4
which is used for channel selection in the Motorola bus interface.
When 16/68# pin is at logic 1, this input is chip select D (active low)
to enable channel D in the device.
When 16/68# pin is at logic 0, this input is not used and should be
connected VCC.
IOW#
(R/W#)
9
18
15
I
CSA#
(CS#)
7
16
13
I
CSB#
(A3)
11
20
17
I
CSC#
(A4)
38
50
64
I
CSD#
(VCC)
42
54
68
I
4
xr
REV. 5.0.2
ST16C654/654D
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
Pin Description
N
AME
INTA
(IRQ#)
64-LQFP 68-PLCC 100-QFP
T
YPE
P
IN
#
P
IN
#
P
IN
#
6
15
12
D
ESCRIPTION
O When 16/68# pin is at logic 1 for Intel bus interface, this ouput
(OD) becomes channel A interrupt output. The output state is defined by
the user and through the software setting of MCR[3]. INTA is set to
the active mode when MCR[3] is set to a logic 1. INTA is set to the
three state mode when MCR[3] is set to a logic 0 (default). See
MCR[3].
When 16/68# pin is at logic 0 for Motorola bus interface, this output
becomes device interrupt output (active low, open drain). An exter-
nal pull-up resistor is required for proper operation.
O
When 16/68# pin is at logic 1 for Intel bus interface, these ouputs
become the interrupt outputs for channels B, C, and D. The output
state is defined by the user through the software setting of MCR[3].
The interrupt outputs are set to the active mode when MCR[3] is set
to a logic 1 and are set to the three state mode when MCR[3] is set
to a logic 0 (default). See MCR[3].
When 16/68# pin is at logic 0 for Motorola bus interface, these out-
puts are unused and will stay at logic zero level. Leave these out-
puts unconnected.
Interrupt Select (active high, input with internal pull-down).
When 16/68# pin is at logic 1 for Intel bus interface, this pin can be
used in conjunction with MCR bit-3 to enable or disable the INT A-D
pins or override MCR bit-3 and enable the interrupt outputs. Inter-
rupt outputs are enabled continuously by making this pin a logic 1.
Making this pin a logic 0 allows MCR bit-3 to enable and disable the
interrupt output pins. In this mode, MCR bit-3 is set to a logic 1 to
enable the continuous output. See MCR bit-3 description for full
detail. This pin must be at logic 0 in the Motorola bus interface
mode. Due to pin limitations on 64 pin packages, this pin is not
available. To cover this limitation, two 64 pin LQFP packages ver-
sions are offered. This pin is bonded to VCC internally in the
ST16C654D so the INT outputs operate in the continuous interrupt
mode. This pin is bonded to GND internally in the ST16C654 and
therefore requires setting MCR bit-3 for enabling the interrupt output
pins.
UART channels A-D Transmitter Ready (active low). The outputs
provide the TX FIFO/THR status for transmit channels A-D. See
Table 5.
If these outputs are unused, leave them unconnected.
INTB
INTC
INTD
(N.C.)
12
37
43
21
49
55
18
63
69
INTSEL
-
65
87
I
TXRDYA#
TXRDYB#
TXRDYC#
TXRDYD#
RXRDYA#
RXRDYB#
RXRDYC#
RXRDYD#
TXRDY#
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
39
5
25
56
81
100
31
50
82
45
O
O
UART channels A-D Receiver Ready (active low). This output pro-
vides the RX FIFO/RHR status for receive channels A-D. See
Table 5.
If these outputs are unused, leave them unconnected.
O
Transmitter Ready (active low). This output is a logically ANDed
status of TXRDY# A-D. See
Table 5.
If this output is unused, leave
it unconnected.
Receiver Ready (active low). This output is a logically ANDed status
of RXRDY# A-D. See
Table 5.
If this output is unused, leave it
unconnected.
RXRDY#
-
38
44
O
5
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