TECHNICAL DATA
IN74HCT241A
Octal 3-State Noninverting Buffer/Line
Driver/Line Receiver
High-Performance Silicon-Gate CMOS
The IN74HCT241A is identical in pinout to the LS/ALS241. The
IN74HCT241A may be used as a level converter for interfacing TTL or
NMOS outputs to High Speed CMOS inputs.
This octal noninverting buffer/line driver/line receiver is designed to
be used with 3-state memory address drivers, clock drivers, and other
bus-oriented systems. The device has noninverting outputs and two
output enables. Enable A is active-low and Enable B is active-high.
•
TTL/NMOS Compatible Input Levels
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 4.5 to 5.5 V
•
Low Input Current: 1.0
µA
ORDERING INFORMATION
IN74HCT241AN Plastic
IN74HCT241ADW SOIC
T
A
= -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Enable
A
PIN 20=V
CC
PIN 10 = GND
L
L
H
A
L
H
X
Output
YA
L
H
Z
Inputs
Enable
B
H
H
L
B
L
H
X
Output
YB
L
H
Z
X = don’t care
Z = high impedance
Rev. 00
IN74HCT241A
MAXIMUM RATINGS
*
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
I
CC
P
D
Tstg
T
L
*
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
Value
-0.5 to +7.0
-1.5 to V
CC
+1.5
-0.5 to V
CC
+0.5
±20
±35
±75
750
500
-65 to +150
260
Unit
V
V
V
mA
mA
mA
mW
°C
°C
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
, V
OUT
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
Min
4.5
0
-55
0
Max
5.5
V
CC
+125
500
Unit
V
V
°C
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range GND≤(V
IN
or
V
OUT
)≤V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
). Unused
outputs must be left open.
Rev. 00
IN74HCT241A
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Symbol
Parameter
Test Conditions
V
Guaranteed Limit
25
°C
to
-55°C
2.0
2.0
0.8
0.8
4.4
5.4
≤85
°C
2.0
2.0
0.8
0.8
4.4
5.4
≤125
°C
2.0
2.0
0.8
0.8
4.4
5.4
Unit
V
IH
Minimum High-
Level Input
Voltage
Maximum Low -
Level Input
Voltage
Minimum High-
Level Output
Voltage
V
OUT
= V
CC
-0.1 V
⎢I
OUT
⎢≤
20
µA
V
OUT
= 0.1 V
⎢I
OUT
⎢ ≤
20
µA
V
IN
= V
IH
⎢I
OUT
⎢ ≤
20
µA
V
IN
= V
IH
⎢I
OUT
⎢ ≤
6.0 mA
4.5
5.5
4.5
5.5
4.5
5.5
V
V
IL
V
V
OH
V
4.5
4.5
5.5
3.98
0.1
0.1
3.84
0.1
0.1
3.7
0.1
0.1
V
V
OL
Maximum Low-
Level Output
Voltage
V
IN
= V
IL
⎢I
OUT
⎢ ≤
20
µA
V
IN
= V
IL
⎢I
OUT
⎢ ≤
6.0 mA
4.5
5.5
5.5
0.26
±0.1
±0.5
0.33
±1.0
±5.0
0.4
±1.0
±10.0
µA
µA
I
IN
I
OZ
Maximum Input
Leakage Current
Maximum three
State Leakage
Current
Maximum
Quiescent Supply
Current
(per Package)
Additional
Quiescent
Supply Current
V
IN
=V
CC
or GND
Output in High-Impedance State
V
IN
= V
IL
or V
IH
V
OUT
=V
CC
or GND
V
IN
=V
CC
or GND
I
OUT
=0µA
I
CC
5.5
4.0
40
160
µA
∆I
CC
V
IN
= 2.4 V, Any One Input
V
IN
=V
CC
or GND, Other Inputs
I
OUT
=0µA
5.5
≥-55°C
2.9
25°C to
125°C
2.4
mA
NOTE: Total Supply Current = I
CC
+
∑∆I
CC
Rev. 00
IN74HCT241A
AC ELECTRICAL CHARACTERISTICS
(V
CC
=5.0 V
±
10%, C
L
=50pF,Input t
r
=t
f
=6.0 ns)
Guaranteed Limit
Symbol
Parameter
25
°C
to
-55°C
23
30
26
12
10
15
≤85°C
≤125°C
Unit
t
PLH
, t
PHL
t
PLZ
, t
PHZ
t
PZH
, t
PZL
t
TLH
, t
THL
C
IN
C
OUT
Maximum Propagation Delay, A to YA or B to
YB (Figures 1 and 3)
Maximum Propagation Delay, Output Enable to
YA or YB (Figures 2 and 4)
Maximum Propagation Delay, Output Enable to
YA or YB (Figures 2 and 4)
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
Maximum Input Capacitance
Maximum Three-State Output Capacitance
(Output in High-Impedance State)
Power Dissipation Capacitance (Per Enable
Output)
29
38
33
15
10
15
35
45
39
18
10
15
ns
ns
ns
ns
pF
pF
Typical @25°C,V
CC
=5.0 V
55
pF
C
PD
Used to determine the no-load dynamic power
consumption:
P
D
=C
PD
V
CC2
f+I
CC
V
CC
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Rev. 00
IN74HCT241A
Figure 3. Test Circuit
Figure 4. Test Circuit
EXPANDED LOGIC DIAGRAM
(1/4 of the Device)
Rev. 00
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