Vectron International's TRU-050 module is a user-configured, phase-locked loop (PLL) solution designed to simplify a wide variety of clock recovery and data retiming,
frequency translation and clock smoothing applications. The device features a phase-lock loop ASIC with a quartz stabilized VCXO for superior stability and jitter performance.
This highly integrated module provides unsurpassed performance, reliability and quality. The proprietary ASIC device includes a refined Phase Detector, a Loop Filter Op-Amp,
a Loss of Signal Alarm with Clock Return to Nominal feature, a VCXO circuit, and an optional 2n divided output.
The ASIC and quartz resonator are housed in a hermetic 16-pin DIL ceramic package with optional thru-hole or surface mount leads. The VCXO frequency (OUT1) and
division factor (OUT2) are factory set in accordance with customer specifications. PLL response is optimized for each application by the selection of three external passive
components. Software is available from Vectron to aid in loop filter component selection and loop response modeling.
is a user-configured phase-locked loop (PLL) integrated circuit. It includes a voltage controlled crystal oscillator (VCXO), an operational amplifier, a phase
detector, and additional integrated functions for use in digital synchronization applications. These applications include timing recovery and data pulse restoration for data
signals, clock frequency translation and smoothing, synchronous distributed clock networks, and clock frequency synthesis.
What is the output of the
phase detector?
The TRU-050 phase detector output
is a DC signal, under locked
conditions, and is nominally 2.5
Volts. The phase error (which is
typically a pulse for digital phase
detectors) is converted to a DC
level, making it easy to design
the loop filter.
TRU-050 Elements
Figure 4.
How long does the
TRU-050 take to detect
a loss of signal?
If there are no transitions on
DATAIN for a period of 256 clock
cycles, LOS is set to a logic 1.
LOS is reset to logic 0 as soon as
there are DATAIN transitions.
Phase Dete c t o r
The phase detector is designed to accept an NRZ data stream at DATAIN (Pin 7- refer to figure 5), but may be used
for clock signals and other data types. The input buffers are designed to switch at a TTL switching threshold of 1.4 V.
The phase detector’s inputs are:
• DATAIN (Pin 7) - the input clock or NRZ data signal
• CLKIN (Pin 9) - the clock signal feedback from the VCXO output OUT1 or OUT2
And the outputs are:
• RCLK (Pin 11) - the regenerated clock signal
• RDATA (Pin 12) - the retimed data signal
• PHO (Pin 6) - the phase detector output
• LOS (Pin 10) - a loss of signal detector
The phase relationship between the regenerated clock signal, RCLK (Pin 11), and the regenerated data signal,
to align the falling edge of the RCLK signal with the center of each RDATA pulse.
For applications where the input clock or data signal, DATAIN, is very low in frequency (<200kHz), clock
information may pass through the phase detector because of its finite low pass characteristic. In applications
such as this, an additional pole may be necessary in the loop filter to attenuate these AC components prior to
the VCXO input. Please contact Vectron’s Applications Engineering staff for further detail.
How is it
manufactured?
The TRU-050 is
assembled in
Figure 6.
“state of the art”
class 100 and class
10,000 clean
rooms using leading
edge, high volume
automation equip-
ment and advanced
ASIC technology.
Figure 7.
Figure 8.
Phase Detector Gain Calculation
The schematic diagram (figure 7) shows a simplified representation of the phase detector's basic error generation function. The actual circuit is more complex and includes
circuitry to reduce the
TRU-050's
dependence on input data duty-cycle. In general, the
TRU-050
is insensitive to duty cycle and duty cycle changes. This circuit provides a
output (V D) DC level which is proportional to the relative phase of DATAIN (Pin 7) and CLKIN (Pin 9). A plot of the output (VD) versus relative phase is shown in figure
8. The slope of the output (VD ) versus relative phase (0 e) is 5V/2π.
The phase detector block also includes an output gain stage which should be considered when calculating the gain of the complete phase detector block. This gain stage
has a gain of 2/3, and converts the differential signal to a single-ended DC output.
I have been studying "Write Your Own CPU" in recent days. . . In the book, the author designed an OpenMIPS teaching version of the processor. Although it is a teaching version, it feels quite complica...
Wzcsapi.lib is set up, and the following header files are also included #include
#include
#include
#include
#include
#include
#include
#includeWhen compiling, the following error message still appears...
There were not many pedestrians on the cold and quiet street, and the shops on the roadside were flashing red festive lights. Compared with the atmosphere of the New Year's Eve festival, the weather w...
Yesterday, Strategy Analytics released its latest survey report, announcing that Xiaomi has become the world's third largest mobile phone manufacturer based on shipments in Q3 2014. Another market res...
With the rapid development of technology, automotive intelligence is increasing at an unprecedented rate. This not only enhances vehicle functionality and comfort, but also places higher deman...[Details]
Multi-touch mobile phone
Multi-touch is a system that can respond to multiple touches on the screen at the same time. Multi-touch phones are divided into capacitive and resistive types. Capaci...[Details]
For healthcare professionals, accurate diagnosis and treatment are crucial for a clear picture of a person's health. However, healthcare professionals often rely on tests at medical facilities, cli...[Details]
Gross profit margin jumped from 13.6% in the first half of last year to 25.9%, almost doubling year-on-year.
On August 21, RoboSense released its interim performance report, in which the...[Details]
On August 22, South Korean media Nate reported on the 20th local time that Samsung Electronics is introducing Hyper Cell technology into its most advanced 2nm process technology, striving to improv...[Details]
1. Multi-channel DAC technology bottleneck
Currently,
the development of multi-channel DAC technology focuses on two core challenges.
First, industrial applications urgently ...[Details]
PowiGaN achieves 95% efficiency at both light and full loads, meeting critical operational and safety requirements.
DARWIN, Australia and SAN JOSE, Calif.,
August 22, 2025 – Powe...[Details]
On August 20, Geely announced its focus on "One Cockpit". Through a unified AI OS architecture, a unified AI Agent, and a unified user ID, it will achieve an All-in-One AI cockpit, create the first...[Details]
Shenzhen Baowei Power Supply high frequency pure sine wave power, communication inverter power supply has two communication interfaces, RS232 and R485 interfaces, their functions and characteristic...[Details]
Wearable technology is taking off, with applications evolving rapidly, from smartwatches to fitness trackers and even smart wigs! Bluetooth Smart is at the center of this revolution. This is the se...[Details]
introduction
With the development of the information superhighway and the internet, broadcast television has become increasingly widespread worldwide. Television information has emerged in var...[Details]
As the electric vehicle industry continues to surge in today's society, while people are concerned about the appearance and interior of new energy vehicles, they are also concerned about the classi...[Details]
This article uses the Allwinner T507 quad-core automotive-grade processor as the development board. This article explains how to configure Ethernet for the T507 development board. Other boards may ...[Details]
• Standard message
1: Speed control
• Standard Telegram
2: Speed Control
• Standard Telegram
3: Speed/Position Control (used when the 1200 is configured as a TO)
...[Details]
The number of new energy vehicles in use is increasing, and there are multiple choices available. New energy vehicles can be divided into hybrid and pure electric, and the types of hybrid include m...[Details]
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
