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TC74AC08P(F)

Description
IC,LOGIC GATE,QUAD 2-INPUT AND,AC-CMOS,DIP,14PIN,PLASTIC
Categorylogic    logic   
File Size221KB,8 Pages
ManufacturerToshiba Semiconductor
Websitehttp://toshiba-semicon-storage.com/
Environmental Compliance
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TC74AC08P(F) Overview

IC,LOGIC GATE,QUAD 2-INPUT AND,AC-CMOS,DIP,14PIN,PLASTIC

TC74AC08P(F) Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
package instructionDIP, DIP14,.3
Reach Compliance Codeunknown
seriesAC
JESD-30 codeR-PDIP-T14
JESD-609 codee3
length19.25 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeAND GATE
MaximumI(ol)0.012 A
Number of functions4
Number of entries2
Number of terminals14
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP14,.3
Package shapeRECTANGULAR
Package formIN-LINE
method of packingTUBE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply3.3/5 V
Prop。Delay @ Nom-Sup11.3 ns
propagation delay (tpd)11.3 ns
Certification statusNot Qualified
Schmitt triggerNO
Maximum seat height4.45 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)2 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfacePURE TIN
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width7.62 mm
Base Number Matches1
TC74AC08P/F/FT
TOSHIBA CMOS Digital Integrated Circuit
Silicon Monolithic
TC74AC08P, TC74AC08F, TC74AC08FT
Quad 2-Input AND Gate
The TC74AC08 is an advanced high speed CMOS 2-INPUT
AND GATE fabricated with silicon gate and double-layer metal
wiring C
2
MOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
The internal circuit is composed of 2 stages including buffer
output, which provide high noise immunity and stable output.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
TC74AC08P
Features
High speed: t
pd
=
3.4 ns (typ.) at V
CC
=
5 V
Low power dissipation: I
CC
=
4
μA
(max) at Ta
=
25°C
High noise immunity: V
NIH
=
V
NIL
=
28% V
CC
(min)
Symmetrical output impedance:
|I
OH
|
=
I
OL
=
24 mA (min)
Capability of driving 50
transmission lines.
Balanced propagation delays: t
pLH
t
pHL
Wide operating voltage range: V
CC
(opr)
=
2 V to 5.5 V
Pin and function compatible with 74F08
TC74AC08F
TC74AC08FT
Weight
DIP14-P-300-2.54
SOP14-P-300-1.27A
TSSOP14-P-0044-0.65A
: 0.96 g (typ.)
: 0.18 g (typ.)
: 0.06 g (typ.)
Start of commercial production
1987-05
1
2014-03-01

TC74AC08P(F) Related Products

TC74AC08P(F) TC74AC08FTEL TC74AC08F(F)
Description IC,LOGIC GATE,QUAD 2-INPUT AND,AC-CMOS,DIP,14PIN,PLASTIC IC GATE AND 4CH 2-INP 14TSSOP IC,LOGIC GATE,QUAD 2-INPUT AND,AC-CMOS,SOP,14PIN,PLASTIC
Is it Rohs certified? conform to - conform to
package instruction DIP, DIP14,.3 - SOP, SOP14,.3
Reach Compliance Code unknown - unknown
series AC - AC
JESD-30 code R-PDIP-T14 - R-PDSO-G14
JESD-609 code e3 - e4
length 19.25 mm - 10.3 mm
Load capacitance (CL) 50 pF - 50 pF
Logic integrated circuit type AND GATE - AND GATE
MaximumI(ol) 0.012 A - 0.012 A
Number of functions 4 - 4
Number of entries 2 - 2
Number of terminals 14 - 14
Maximum operating temperature 85 °C - 85 °C
Minimum operating temperature -40 °C - -40 °C
Package body material PLASTIC/EPOXY - PLASTIC/EPOXY
encapsulated code DIP - SOP
Encapsulate equivalent code DIP14,.3 - SOP14,.3
Package shape RECTANGULAR - RECTANGULAR
Package form IN-LINE - SMALL OUTLINE
method of packing TUBE - TUBE
Peak Reflow Temperature (Celsius) NOT SPECIFIED - NOT SPECIFIED
power supply 3.3/5 V - 3.3/5 V
Prop。Delay @ Nom-Sup 11.3 ns - 11.3 ns
propagation delay (tpd) 11.3 ns - 11.3 ns
Certification status Not Qualified - Not Qualified
Schmitt trigger NO - NO
Maximum seat height 4.45 mm - 1.9 mm
Maximum supply voltage (Vsup) 5.5 V - 5.5 V
Minimum supply voltage (Vsup) 2 V - 2 V
Nominal supply voltage (Vsup) 5 V - 5 V
surface mount NO - YES
technology CMOS - CMOS
Temperature level INDUSTRIAL - INDUSTRIAL
Terminal surface PURE TIN - Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form THROUGH-HOLE - GULL WING
Terminal pitch 2.54 mm - 1.27 mm
Terminal location DUAL - DUAL
Maximum time at peak reflow temperature NOT SPECIFIED - NOT SPECIFIED
width 7.62 mm - 5.3 mm

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