PALCE16V8H-15JC/4 datasheet, PDF

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PALCE16V8H-15JC/4: DescriptionEE PLD, 15ns, PAL-Type, CMOS, PQCC20, PLASTIC, LCC-20; CategoryProgrammable logic devices Programmable logic; File Size493KB，32 Pages; ManufacturerVantis Corporation

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PALCE16V8H-15JC/4 Overview

EE PLD, 15ns, PAL-Type, CMOS, PQCC20, PLASTIC, LCC-20

PALCE16V8H-15JC/4 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
package instruction	PLASTIC, LCC-20
Reach Compliance Code	unknown
Architecture	PAL-TYPE
maximum clock frequency	50 MHz
JESD-30 code	S-PQCC-J20
JESD-609 code	e0
Dedicated input times	10
Number of I/O lines	8
Number of entries	18
Output times	8
Number of product terms	64
Number of terminals	20
Maximum operating temperature	70 °C
Minimum operating temperature
organize	10 DEDICATED INPUTS, 8 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC20,.4SQ
Package shape	SQUARE
Package form	CHIP CARRIER
power supply	5 V
Programmable logic type	EE PLD
propagation delay	15 ns
Certification status	Not Qualified
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Base Number Matches	1

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PALCE16V8

PALCE16V8Z

COM’L:H-5/7/10/15/25, Q-10/15/25 IND:H-10/25, Q-20/25

COM’L:-25

IND:-12/15/25

PALCE16V8 and PALCE16V8Z Families

EE CMOS (Zero-Power) 20-Pin Universal

Programmable Array Logic

DISTINCTIVE CHARACTERISTICS

Pin and function compatible with all 20-pin PAL

devices

Electrically erasable CMOS technology provides reconﬁgurable logic and full testability

High-speed CMOS technology

— 5-ns propagation delay for “-5” version

— 7.5-ns propagation delay for “-7” version

Direct plug-in replacement for the PAL16R8 series

Outputs programmable as registered or combinatorial in any combination

Peripheral Component Interconnect (PCI) compliant

Programmable output polarity

Programmable enable/disable control

Preloadable output registers for testability

Automatic register reset on power up

Cost-effective 20-pin plastic DIP, PLCC, and SOIC packages

Extensive third-party software and programmer support

Fully tested for 100% programming and functional yields and high reliability

5-ns version utilizes a split leadframe for improved performance

PAL Devices

GENERAL DESCRIPTION

The PALCE16V8 is an advanced PAL device built with low-power, high-speed, electrically-

erasable CMOS technology. It is functionally compatible with all 20-pin GAL devices. The

macrocells provide a universal device architecture. The PALCE16V8 will directly replace the

PAL16R8, with the exception of the PAL16C1.

The PALCE16V8Z provides zero standby power and high speed. At 30-µA maximum standby

current, the PALCE16V8Z allows battery-powered operation for an extended period.

The PALCE16V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to

implement complex logic functions easily and efﬁciently. Multiple levels of combinatorial logic

can always be reduced to sum-of-products form, taking advantage of the very wide input gates

available in PAL devices. The equations are programmed into the device through ﬂoating-gate

cells in the AND logic array that can be erased electrically.

The ﬁxed OR array allows up to eight data product terms per output for logic functions. The

sum of these products feeds the output macrocell. Each macrocell can be programmed as

registered or combinatorial with an active-high or active-low output. The output conﬁguration

is determined by two global bits and one local bit controlling four multiplexers in each

macrocell.

Publication#

16493

Amendment/0

Rev:

Issue Date:

November 1998

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