MX25L3205A
Macronix NBit
TM
Memory Family
32M-BIT [x 1] CMOS SERIAL eLiteFlash
TM
MEMORY
FEATURES
GENERAL
• Serial Peripheral Interface (SPI) compatible -- Mode 0
and Mode 3
• 33,554,432 x 1 bit structure
• 64 Equal Sectors with 64K byte each
- Any sector can be erased
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
• Low Vcc write inhibit is from 1.5V to 2.5V
PERFORMANCE
• High Performance
- Fast access time: 50MHz serial clock (30pF + 1TTL
Load)
- Fast program time: 3ms/page (typical, 256-byte per
page)
- Fast erase time: 1s/sector (typical, 64K-byte per
sector) and 64s/chip (typical)
- Acceleration mode:
- Program time: 2.4ms/page (typical)
- Erase time: 0.8s/sector (typical) and 51s/chip
(typical)
• Low Power Consumption
- Low active read current: 30mA (max.) at 50MHz
- Low active programming current: 30mA (max.)
- Low active erase current: 38mA (max.)
- Low standby current: 50uA (max.)
- Deep power-down mode 1uA (typical)
• Minimum 10K erase/program cycle for array
• Minimum 100K erase/program cycle for additional 4Kb
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Auto Erase and Auto Program Algorithm
-
Automatically erases and verifies data at selected
sector
-
Automatically programs and verifies data at selected
page by an internal algorithm that automatically times
the program pulse widths (Any page to be programed
should have page in the erased state first)
•
Status Register Feature
•
Electronic Identification
-
JEDEC 2-byte Device ID
- RES command, 1-byte Device ID
- REMS command, ADD=00H will output the
manufacturer's ID first and ADD=01H will output device
ID first
•
Additional 4Kb sector independent from main memory
for parameter storage to eliminate EEPROM from
system
HARDWARE FEATURES
•
SCLK Input
-
Serial clock input
• SI Input
-
Serial Data Input
• SO/PO7
- Serial Data Output or Parallel mode Data output/input
• WP#/ACC Pin
-
Hardware write protection and Program/erase accel-
eration
• HOLD# pin
-
pause the chip without disselecting the chip (not for
parallel mode, please connect HOLD# pin to VCC dur-
ing parallel mode)
• PO0~PO6
- for parallel mode data output/input
• PACKAGE
-
16-pin SOP (300mil)
- 8-land SON (8x6mm)
-
All Pb-free devices are RoHS Compliant
P/N: PM1243
REV. 1.2, NOV. 06, 2006
1
MX25L3205A
GENERAL DESCRIPTION
The MX25L3205A is a CMOS 33,554,432 bit serial
eLiteFlash
TM
Memory, which is configured as 4,194,304 x
8 internally. The MX25L3205A features a serial peripheral
interface and software protocol allowing operation on a
simple 3- wire bus. The three bus signals are a clock input
(SCLK), a serial data input (SI), and a serial data output
(SO). SPI access to the device is enabled by CS# input.
The MX25L3205A provide sequential read operation on
whole chip. User may start to read from any byte of the
array. While the end of the array is reached, the device will
wrap around to the beginning of the array and continuously
outputs data until CS# goes high.
After program/erase command is issued, auto program/
erase algorithms which program/erase and verify the
specified page locations will be executed. Program com-
mand is executed on a page (256 bytes) basis, and erase
command is executed on both chip and sector (64K bytes)
basis.
To provide user with ease of interface, a status register is
included to indicate the status of the chip. The status read
command can be issued to detect completion and error
flag status of a program or erase operation.
To increase user's factory throughputs, a parallel mode is
provided. The performance of read/program is dramatically
improved than serial mode on programmer machine.
When the device is not in operation and CS# is high, it is
put in standby mode and draws less than 50uA DC current.
The additional 4Kb sector with 100K erase/program endur-
ance cycles is suitable for parameter storage and replaces
the EEPROM on system.
The MX25L3205A utilizes MXIC's proprietary memory cell
which reliably stores memory contents even after 10K
program and erase cycles.
PIN CONFIGURATIONS
16-PIN SOP (300 mil)
HOLD#
VCC
NC
PO2
PO1
PO0
CS#
SO/PO7
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SCLK
SI
PO6
PO5
PO4
PO3
GND
WP#/ACC
PIN DESCRIPTION
SYMBOL
CS#
SI
SO/PO7(1)
SCLK
HOLD#(2)
WP#/ACC
DESCRIPTION
Chip Select
Serial Data Input
Serial Data Output or Parallel Data
output/input
Clock Input
Hold, to pause the serial communication
(HOLD# is not for parallel mode)
Write Protection: connect to GND;
12V for program/erase acceleration:
connect to 12V
+ 3.3V Power Supply
Ground
Parallel data output/input (PO0~PO6 can
be connected to NC in serial mode)
No Internal Connection
8-LAND SON (8x6mm)
CS#
SO
WP#
GND
1
2
3
4
8
7
6
5
VCC
HOLD#
SCLK
SI
VCC
GND
PO0~PO6
NC
Note:
1. PO0~PO7 are not provided on 8-LAND SON package.
2. HOLD# is recommended to connect to VCC during
parallel mode.
P/N: PM1243
REV. 1.2, NOV. 06, 2006
2
MX25L3205A
BLOCK DIAGRAM
additional 4Kb
Address
Generator
X-Decoder
Memory Array
SI
Data
Register
Y-Decoder
SRAM
Buffer
Sense
Amplifier
HV
Generator
SO
Output
Buffer
CS#, ACC,
WP#,HOLD#
Mode
Logic
State
Machine
SCLK
Clock Generator
P/N: PM1243
3
REV. 1.2, NOV. 06, 2006
MX25L3205A
DATA PROTECTION
The MX25L3205A are designed to offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power
transition. During power up the device automatically resets
the state machine in the Read mode. In addition, with its
control register architecture, alteration of the memory
contents only occurs after successful completion of
specific command sequences. The device also
incorporates several features to prevent inadvertent write
cycles resulting from VCC power-up and power-down
transition or system noise.
•
Power-on reset and tPUW: to avoid sudden power
switch by system power supply transition, the power-
on reset and tPUW (internal timer) may protect the
Flash.
other command to change data. The WEL bit will return
to reset stage under following situation:
- Power-up
- Write Disable (WRDI) command completion
- Write Status Register (WRSR) command completion
- Page Program (PP) command completion
- Sector Erase (SE) command completion
- Block Erase (BE) command completion
- Chip Erase (CE) command completion
•
Software Protection Mode (SPM): by using BP0-BP2
bits to set the part of Flash protected from data change.
Hardware Protection Mode (HPM): by using WP# going
low to protect the BP0-BP2 bits and SRWD bit from
data change.
Deep Power Down Mode: By entering deep power down
mode, the flash device also is under protected from
writing all commands except Release from deep power
down mode command (RDP) and Read Electronic
Signature command (RES).
•
• Valid command length checking: The command length
will be checked whether it is at byte base and com-
pleted on byte boundary.
• Write Enable (WREN) command: WREN command is
required to set the Write Enable Latch bit (WEL) before
•
P/N: PM1243
4
REV. 1.2, NOV. 06, 2006
MX25L3205A
Table 1. Protected Area Sizes
Status bit
BP2
0
0
0
0
1
1
1
1
BP1
0
0
1
1
0
0
1
1
BP0
0
1
0
1
0
1
0
1
Protection Area
32Mb
None
Upper 64th (Sector 63)
Upper 32nd (two sectors: 62 and 63)
Upper sixteenth (four sectors: 60 to 63)
Upper eighth (eight sectors: 56 to 63)
Upper quarter (sixteen sectors: 48 to 63)
Upper half (thirty-two sectors: 32 to 63)
All
Note:
1. The device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0.
P/N: PM1243
5
REV. 1.2, NOV. 06, 2006
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