V58C2512164SDLJ5BE datasheet, PDF

Datasheet> All Categories > storage> storage> V58C2512164SDLJ5BE

V58C2512164SDLJ5BE: DescriptionDDR DRAM, 32MX16, CMOS, PBGA60, GREEN, MO-207, FBGA-60; Categorystorage storage; File Size1MB，61 Pages; ManufacturerProMOS Technologies Inc

Download Datasheet Parametric View All

V58C2512164SDLJ5BE Overview

DDR DRAM, 32MX16, CMOS, PBGA60, GREEN, MO-207, FBGA-60

V58C2512164SDLJ5BE Parametric

Parameter Name	Attribute value
Parts packaging code	DSBGA
package instruction	TBGA,
Contacts	60
Reach Compliance Code	compliant
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Other features	AUTO/SELF REFRESH
JESD-30 code	R-PBGA-B60
length	12 mm
memory density	536870912 bit
Memory IC Type	DDR DRAM
memory width	16
Number of functions	1
Number of ports	1
Number of terminals	60
word count	33554432 words
character code	32000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
organize	32MX16
Package body material	PLASTIC/EPOXY
encapsulated code	TBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE
Certification status	Not Qualified
Maximum seat height	1.2 mm
self refresh	YES
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	10 mm
Base Number Matches	1

Preview

Download Datasheet

View All

V58C2512(804/404/164)SD

HIGH PERFORMANCE 512 Mbit DDR SDRAM

4 BANKS X 16Mbit X 8 (804)

4 BANKS X 32Mbit X 4 (404)

4 BANKS X 8Mbit X 16 (164)

DDR500

Clock Cycle Time (t

CK2.5

)

Clock Cycle Time (t

CK3

)

System Frequency (f

CK max

)

4ns

250 MHz

DDR400

6ns

5ns

200 MHz

DDR333

6ns

166 MHz

DDR266

7.5ns

133 MHz

Features

Description

The V58C2512(804/404/164)SD is a four bank DDR

DRAM organized as 4 banks x 16Mbit x 8 (804), 4 banks x

32Mbit x 4 (404), 4 banks x 8Mbit x 16 (164). The

V58C2512(804/404/164)SD achieves high speed data

transfer rates by employing a chip architecture that

prefetches multiple bits and then synchronizes the output

data to a system clock.

All of the control, address, circuits are synchronized

with the positive edge of an externally supplied clock. I/O

transactions are occurring on both edges of DQS.

Operating the four memory banks in an interleaved

fashion allows random access operation to occur at a

higher rate than is possible with standard DRAMs. A se-

quential and gapless data rate is possible depending on

burst length, CAS latency and speed grade of the device.

High speed data transfer rates with system frequency

up to 250MHz

Data Mask for Write Control

Four Banks controlled by BA0 & BA1

Programmable CAS Latency: 2.5, 3

Programmable Wrap Sequence: Sequential

or Interleave

Programmable Burst Length:

2, 4, 8 for Sequential Type

2, 4, 8 for Interleave Type

Automatic and Controlled Precharge Command

Power Down Mode

Auto Refresh and Self Refresh

Refresh Interval: 8192 cycles/64 ms

Available in 60 Ball FBGA AND 66 Pin TSOP II

SSTL-2 Compatible I/Os

Double Data Rate (DDR)

Bidirectional Data Strobe (DQS) for input and output

data, active on both edges

On-Chip DLL aligns DQ and DQs transitions with CK

transitions

Differential clock inputs CK and CK

Power Supply 2.5V ± 0.2V

tRAS lockout supported

Concurrent auto precharge option is supported

Device Usage Chart

Operating

Temperature

Range

0°C to 70°C

Package Outline

JEDEC 66 TSOP II

60 FBGA

•

CK Cycle Time (ns)

-4

•

Power

-75

•

-5

•

-6

•

Std.

•

Temperature

Mark

Blank

V58C2512(804/404/164)SD Rev.1.6 May 2010

Recommended Resources

Composite complementary symmetrical push-pull output stage circuit

Crystal diode-capacitor double boost circuit (2)

Full wave control circuit of series motor

Bistable single-sided trigger circuit

Computer motherboard circuit diagram 815 2_01

Traffic light control circuit diagram

Question about ADC12: Is it true that the running time of the ADC12 interrupt program cannot exceed the sampling time interval set by ADC12SHT0?...; zzbaizhi Microcontroller MCU

Pseudo-instructions supported by ARM assembler1: 4.1.1 Symbol Definition Pseudo-instructions Symbol Definition Pseudo-instructions are used to define variables in the ARM assembler, assign values to variables, and define register aliases. Common sym...; liuyong1989 MCU

The 11th software exam started, and I only read two-thirds of the book: I have a lot of free time, so I thought about what kind of certificate I should take. I checked online and found out that I need to take the Intermediate Software Engineer exam due to work reasons. I ...; 懒猫爱飞 Talking

Does the ripple of the power supply have any effect on the output of the filter?: For example, for the simple low-pass filter below, the actual power supply ripple is about ±40mV. How much impact will this ripple have on the output signal of the filter?...; 飞絮 Analog electronics

How to do it?: I really don't know how to do it, can someone tell me, thank you!...; 曹伟1993 Suggestions & Announcements

Is there any source code for displaying jpeg under wince?: It is best to display the buffer, not the loadfile....; kedou000007 Embedded System

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components