Freescale Semiconductor
Data Sheet: Advance Information
Document Number: MPC5604BC
Rev. 8, 11/2010
MPC5604B/C
MAPBGA–225
208
15 mm x 15 mm
MAPBGA
(17 x 17 x 1.7 mm)
QFN12
144 LQFP
##_mm_x_##mm
(20 x 20 x 1.4 mm)
MPC5604B/C
Microcontroller Data Sheet
32-bit MCU family built on the Power Architecture
®
for
automotive body electronics applications
Features
•
Single issue, 32-bit CPU core complex (e200z0)
— Compliant with the Power Architecture
®
embedded category
— Includes an instruction set enhancement
allowing variable length encoding (VLE) for
code size footprint reduction. With the optional
encoding of mixed 16-bit and 32-bit
instructions, it is possible to achieve significant
code size footprint reduction.
Up to 512 KB on-chip code flash supported with the
flash controller
64 (4 × 16) KB on-chip data flash memory with ECC
Up to 48 KB on-chip SRAM
Memory protection unit (MPU) with 8 region
descriptors and 32-byte region granularity
Interrupt controller (INTC) with 148 interrupt
vectors, including 16 external interrupt sources and
18 external interrupt/wakeup sources
Frequency modulated phase-locked loop (FMPLL)
Crossbar switch architecture for concurrent access to
peripherals, flash, or RAM from multiple bus
masters
Boot assist module (BAM) supports internal flash
programming via a serial link (CAN or SCI)
Timer supports input/output channels providing a
range of 16-bit input capture, output compare, and
pulse width modulation functions (eMIOS-lite)
10-bit analog-to-digital converter (ADC)
3 serial peripheral interface (DSPI) modules
1
2
3
100 LQFP
(14 x 14 x 1.4 mm)
SOT-343R
##_mm_x_##mm
TBD
PKG-TBD
## mm x ## mm
64 LQFP
(10 x 10 x 1.4 mm)
4
•
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•
5
6
7
•
•
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . 8
3.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.2 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . . 33
4.3 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . 35
4.5 Recommended operating conditions . . . . . . . . . . . . . . 36
4.6 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . 38
4.7 I/O pad electrical characteristics . . . . . . . . . . . . . . . . . 40
4.8 RESET electrical characteristics . . . . . . . . . . . . . . . . . 51
4.9 Power management electrical characteristics . . . . . . . 53
4.10 Low voltage domain power consumption . . . . . . . . . . . 56
4.11 Flash memory electrical characteristics . . . . . . . . . . . . 58
4.12 Electromagnetic compatibility (EMC) characteristics . . 62
4.13 Fast external crystal oscillator (4 to 16 MHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.14 Slow external crystal oscillator (32 kHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.15 FMPLL electrical characteristics. . . . . . . . . . . . . . . . . . 69
4.16 Fast internal RC oscillator (16 MHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.17 Slow internal RC oscillator (128 kHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.18 ADC electrical characteristics. . . . . . . . . . . . . . . . . . . . 72
4.19 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.1 Package mechanical data. . . . . . . . . . . . . . . . . . . . . . . 89
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . 100
•
•
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2009, 2010. All rights reserved.
Introduction
•
•
•
•
•
•
•
•
•
•
Up to 4 serial communication interface (LINFlex) modules
Up to 6 enhanced full CAN (FlexCAN) modules with configurable buffers
1 inter IC communication interface (I
2
C) module
Up to 123 configurable general purpose pins supporting input and output operations (package dependent)
Real Time Counter (RTC) with clock source from 128 kHz or 16 MHz internal RC oscillator supporting autonomous
wakeup with 1 ms resolution with max timeout of 2 seconds
Up to 6 periodic interrupt timers (PIT) with 32-bit counter resolution
1 System Module Timer (STM)
Nexus development interface (NDI) per IEEE-ISTO 5001-2003 Class Two Plus standard
Device/board boundary Scan testing supported with per Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1)
On-chip voltage regulator (VREG) for regulation of input supply for all internal levels
1
1.1
Introduction
Document overview
This document describes the features of the family and options available within the family members, and highlights important
electrical and physical characteristics of the device. To ensure a complete understanding of the device functionality, refer also
to the device reference manual and errata sheet.
1.2
Description
The MPC5604B/C is a family of next generation microcontrollers built on the Power Architecture
®
embedded category.
The MPC5604B/C family of 32-bit microcontrollers is the latest achievement in integrated automotive application controllers.
It belongs to an expanding family of automotive-focused products designed to address the next wave of body electronics
applications within the vehicle. The advanced and cost-efficient host processor core of this automotive controller family
complies with the Power Architecture embedded category and only implements the VLE (variable-length encoding) APU,
providing improved code density. It operates at speeds of up to 64 MHz and offers high performance processing optimized for
low power consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and
is supported with software drivers, operating systems and configuration code to assist with users implementations.
MPC5604B/C Microcontroller Data Sheet, Rev. 8
2
Freescale Semiconductor
Table 1. MPC5604B/C device comparison
1
(continued)
Device
Feature
MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC560
02BxLH 02BxLL 02BxLQ 02CxLH 02CxLL 03BxLH 03BxLL 03BxLQ 03CxLH 03CxLL 04BxLH 04BxLL 04BxLQ 04CxLH 04CxLL 4BxMG
64
LQFP
9
100
LQFP
144
LQFP
64
LQFP
9
100
LQFP
64
LQFP
9
100
LQFP
144
LQFP
64
LQFP
9
100
LQFP
64
LQFP
9
100
LQFP
144
LQFP
64
LQFP
9
100
LQFP
208
MAPBG
A
10
Introduction
4
Package
1
Feature set dependent on selected peripheral multiplexing—table shows example implementation
2
Based on 125 °C ambient operating temperature
3
Refer to eMIOS section of device reference manual for information on the channel configuration and functions
4
IC - Input Capture; OC - Output Compare; PWM - Pulse Width Modulation; MC - Modulus counter
5
SCI0, SCI1 and SCI2 are available. SCI3 is not available.
6
CAN0, CAN1 are available. CAN2, CAN3, CAN4 and CAN5 are not available.
7
CAN0, CAN1 and CAN2 are available. CAN3, CAN4 and CAN5 are not available.
8
I/O count based on multiplexing with peripherals
9
All 64 LQFPinformation is indicative and must be confirmed during silicon validation.
10
208 MAPBGA available only as development package for Nexus2+
MPC5604B/C Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
Block diagram
2
Block diagram
Figure 1. MPC5604B/C series block diagram
JTAG
JTAG port
Nexus port
Nexus
NMI
SIUL
Voltage
regulator
NMI
Interrupt requests
from peripheral
blocks
INTC
Clocks
FMPLL
CMU
Instructions
e200z0h
(Master)
Data
Nexus 2+
(Master)
64-bit 2 x 3 Crossbar Switch
SRAM
48 KB
Code Flash Data Flash
512 KB
64 KB
Figure 1
shows a top-level block diagram of the MPC5604B/C device series.
SRAM
controller
MPU
Flash
controller
(Slave)
(Slave)
(Slave)
MPU
registers
RTC
STM
SWT
ECSM
PIT
MC_RGM MC_CGM MC_ME
MC_PCU
BAM
SSCM
Peripheral bridge
Interrupt
request
SIUL
Reset control
External
interrupt
request
IMUX
GPIO and
pad control
36 Ch.
ADC
CTU
2x
eMIOS
4x
LINFlex
3x
DSPI
I
2
C
6x
FlexCAN
WKPU
I/O
Legend:
ADC
BAM
FlexCAN
CMU
CTU
DSPI
eMIOS
FMPLL
I
2
C
IMUX
INTC
JTAG
LINFlex
ECSM
MC_CGM
...
...
...
...
...
Interrupt
request with
wakeup
functionality
Analog-to-Digital Converter
Boot Assist Module
Controller Area Network
Clock Monitor Unit
Cross Triggering Unit
Deserial Serial Peripheral Interface
Enhanced Modular Input Output System
Frequency-Modulated Phase-Locked Loop
Inter-integrated Circuit Bus
Internal Multiplexer
Interrupt Controller
JTAG controller
Serial Communication Interface (LIN support)
Error Correction Status Module
Clock Generation Module
MC_ME
MC_PCU
MC_RGM
MPU
Nexus
NMI
PIT
RTC
SIUL
SRAM
SSCM
STM
SWT
WKPU
Mode Entry Module
Power Control Unit
Reset Generation Module
Memory Protection Unit
Nexus Development Interface (NDI) Level
Non-Maskable Interrupt
Periodic Interrupt Timer
Real-Time Clock
System Integration Unit Lite
Static Random-Access Memory
System Status Configuration Module
System Timer Module
Software Watchdog Timer
Wakeup Unit
MPC5604B/C Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
5
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