D ts e t
aa h e
R c e t r lc r nc
o h se Ee to is
Ma u a t r dCo o e t
n fc u e
mp n n s
R c e tr b a d d c mp n ns ae
o h se rn e
o oet r
ma ua trd u ig ete dewaes
n fcue sn i r i/ fr
h
p rh s d f m te oiia s p l r
uc a e r
o h r n l u pi s
g
e
o R c e tr waes rce td f m
r o h se
fr e rae r
o
te oiia I. Al rce t n ae
h
r nl P
g
l e rai s r
o
d n wi tea p o a o teOC
o e t h p rv l f h
h
M.
P r aetse u igoiia fcoy
at r e td sn r n la tr
s
g
ts p o rmso R c e tr e eo e
e t rga
r o h se d v lp d
ts s lt n t g aa te p o u t
e t oui s o u rne
o
rd c
me t o e c e teOC d t s e t
es r x e d h
M aa h e.
Qu l yOv riw
ai
t
e ve
• IO- 0 1
S 90
•A 92 cr ct n
S 1 0 et ai
i
o
• Qu l e Ma ua trr Ls (
ai d
n fcues it QML MI- R -
) LP F
385
53
•C a sQ Mitr
ls
lay
i
•C a sVS a eL v l
ls
p c ee
• Qu l e S p l r Ls o D sr uos( L )
ai d u pi s it f it b tr QS D
e
i
•R c e trsacic l u pir oD A a d
o h se i
r ia s p l t L n
t
e
me t aln u t a dD A sa d r s
es lid sr n L tn ad .
y
R c e tr lcrnc , L i c mmi e t
o h se Ee t is L C s o
o
tdo
t
s p ligp o u t ta s t f c so r x e t-
u pyn rd cs h t ai y u tme e p ca
s
t n fr u lya daee u loto eoiial
i s o q ai n r q a t h s r n l
o
t
g
y
s p l db id sr ma ua trr.
u pi
e yn ut
y n fcues
T eoiia ma ua trr d ts e t c o a yn ti d c me t e e t tep r r n e
h r n l n fcue’ aa h e a c mp n ig hs o u n r cs h ef ma c
g
s
o
a ds e ic t n o teR c e tr n fcue v rino ti d vc . o h se Ee t n
n p c ai s f h o h se ma ua trd eso f hs e ie R c e tr lcr -
o
o
isg aa te tep r r n eo i s mio d co p o u t t teoiia OE s e ic -
c u rne s h ef ma c ft e c n u tr rd cs o h r n l M p c a
o
s
g
t n .T pc lv le aefr eee c p r o e o l. eti mii m o ma i m rt g
i s ‘y ia’ au s r o rfrn e up s s ny C r n nmu
o
a
r xmu ai s
n
ma b b s do p o u t h rceiain d sg , i lt n o s mpetsig
y e a e n rd c c aa tr t , e in smuai , r a l e t .
z o
o
n
© 2 1 R cetr l t n s LC Al i t R sre 0 1 2 1
0 3 ohs E cr i , L . lRg s eevd 7 1 0 3
e e oc
h
T l r m r, l s v iw wrcl . m
o e n oe p ae it w . e c o
a
e
s
o ec
MC9S08JM60 Series Features
8-Bit HCS08 Central Processor Unit (CPU)
•
•
•
•
•
48-MHz HCS08 CPU (central processor unit)
24-MHz internal bus frequency
HC08 instruction set with added BGND instruction
Background debugging system
Breakpoint capability to allow single breakpoint
setting during in-circuit debugging (plus two more
breakpoints in on-chip debug module)
• In-circuit emulator (ICE) debug module containing
two comparators and nine trigger modes. Eight
deep FIFO for storing change-of-flow addresses
and event-only data. Debug module supports both
tag and force breakpoints.
• Support for up to 32 interrupt/reset sources
•
SPI
— Two 8- or 16-bit selectable serial peripheral
interface modules with a receive data buffer
hardware match function
•
IIC
— Inter-integrated circuit bus module to
operate at up to 100 kbps with maximum bus
loading; multi-master operation; programmable
slave address; interrupt-driven byte-by-byte data
transfer; 10-bit addressing and broadcast modes
support
•
Timers
— One 2-channel and one 6-channel
16-bit timer/pulse-width modulator (TPM)
modules: Selectable input capture, output
compare, and edge-aligned PWM capability on
each channel. Each timer module may be
configured for buffered, centered PWM (CPWM)
on all channels
•
KBI
— 8-pin keyboard interrupt module
•
RTC
— Real-time counter with binary- or
decimal-based prescaler
Memory Options
• Up to 60 KB of on-chip in-circuit programmable
flash memory with block protection and security
options
• Up to 4 KB of on-chip RAM
• 256 bytes of USB RAM
Input/Output
• Up to 51 general-purpose input/output pins
• Software selectable pullups on ports when used
as inputs
• Software selectable slew rate control on ports
when used as outputs
• Software selectable drive strength on ports when
used as outputs
• Master reset pin and power-on reset (POR)
• Internal pullup on RESET, IRQ, and BKGD/MS
pins to reduce customer system cost
Clock Source Options
• Clock source options include crystal, resonator,
external clock
• MCG (multi-purpose clock generator) — PLL and
FLL; internal reference clock with trim adjustment
System Protection
• Optional computer operating properly (COP) reset
with option to run from independent 1-kHz internal
clock source or the bus clock
• Low-voltage detection with reset or interrupt
• Illegal opcode detection with reset
• Illegal address detection with reset
Package Options
•
•
•
•
64-pin quad flat package (QFP)
64-pin low-profile quad flat package (LQFP)
48-pin quad flat no-lead (QFN)
44-pin low-profile quad flat package (LQFP)
Power-Saving Modes
• Wait plus two stops
Peripherals
•
USB —
USB 2.0 full-speed (12 Mbps) device
controller with dedicated on-chip USB transceiver,
3.3-V regulator and USBDP pull-up resister;
supports control, interrupt, isochronous, and bulk
transfers; supports endpoint 0 and up to 6
additional endpoints; endpoints 5 and 6 can be
combined to provide double buffering capability
•
ADC
— 12-channel, 12-bit analog-to-digital
converter with automatic compare function;
internal temperature sensor
•
ACMP
— Analog comparator with option to
compare to internal reference; operation in stop3
mode
•
SCI
— Two serial communications interface
modules with optional 13-bit break LIN extensions
京公网安备 11010802033920号
EEWORLD
