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IDT70V37L15PFI

Description
Dual-Port SRAM, 32KX18, 15ns, CMOS, PQFP100, TQFP-100
Categorystorage    storage   
File Size151KB,17 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

IDT70V37L15PFI Overview

Dual-Port SRAM, 32KX18, 15ns, CMOS, PQFP100, TQFP-100

IDT70V37L15PFI Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
Parts packaging codeQFP
package instructionLFQFP,
Contacts100
Reach Compliance Codecompliant
ECCN code3A991.B.2.B
Maximum access time15 ns
Other featuresINTERRUPT FLAG
JESD-30 codeS-PQFP-G100
JESD-609 codee0
length14 mm
memory density589824 bit
Memory IC TypeDUAL-PORT SRAM
memory width18
Humidity sensitivity level3
Number of functions1
Number of terminals100
word count32768 words
character code32000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize32KX18
Package body materialPLASTIC/EPOXY
encapsulated codeLFQFP
Package shapeSQUARE
Package formFLATPACK, LOW PROFILE, FINE PITCH
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)240
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTIN LEAD
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature20
width14 mm
Base Number Matches1
HIGH-SPEED 3.3V
32K x 18 DUAL-PORT
STATIC RAM
.eatures
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 15/20ns (max.)
– Industrial: 20ns (max.)
Low-power operation
– IDT70V37L
Active: 440mW (typ.)
Standby: 660µW (typ.)
Dual chip enables allow for depth expansion without
external logic
IDT70V37 easily expands data bus width to 36 bits or
more using the Master/Slave select when cascading more
than one device
x
x
x
x
PRELIMINARY
IDT70V37L
x
x
x
x
x
x
x
x
x
x
M/S = V
IH
for
BUSY
output flag on Master,
M/S = V
IL
for
BUSY
input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Separate upper-byte and lower-byte controls for multi-
plexed bus and bus matching compatibility
LVTTL-compatible, single 3.3V (±0.3V) power supply
Available in a 100-pin TQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
.unctional Block Diagram
R/
W
L
UB
L
CE
0L
CE
1L
OE
L
LB
L
R/
W
R
UB
R
CE
0R
CE
1R
OE
R
LB
R
I/O
9-17L
I/O
0-8L
BUSY
L
(1,2)
A
14L
A
0L
32Kx18
MEMORY
ARRAY
70V37
15
15
I/O
9-17R
I/O
Control
I/O
Control
I/O
0-8R
BUSY
R
A
14R
A
0R
(1,2)
.
Address
Decoder
Address
Decoder
CE
0L
CE
1L
OE
L
R/W
L
SEM
L
INT
L
(2)
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
0R
CE
1R
OE
R
R/W
R
SEM
R
(2)
INT
R
4851 drw 01
M/S
(1)
NOTES:
1.
BUSY
is an input as a Slave (M/S=V
IL
) and an output when it is a Master (M/S=V
IH
).
2.
BUSY
and
INT
are non-tri-state totem-pole outputs (push-pull).
JANUARY 2002
DSC-4851/2
1
©2002 Integrated Device Technology, Inc.
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