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PL611S-28-XXXTC-R

Description
Clock Generator,
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size312KB,8 Pages
ManufacturerPLL (PhaseLink Corporation)
Download Datasheet Parametric Compare View All

PL611S-28-XXXTC-R Overview

Clock Generator,

PL611S-28-XXXTC-R Parametric

Parameter NameAttribute value
package instruction,
Reach Compliance Codeunknown
Base Number Matches1
(Preliminary)
PL611s-28
1.8V-3.3V PicoPLL
TM
, World’s Smallest Programmable Clock
FEATURES
Designed for Very Low-Power applications
Input Frequency:
o
Fundamental Crystal: 10MHz to 50MHz
o
Reference Input: 1MHz to 200MHz
Accepts >0.1V reference signal input voltage
Output Frequency:
o
<65MHz @ 1.8V operation
o
<90MHz @ 2.5V operation
o
<125MHz @ 3.3V operation
Disabled outputs programmable as HiZ or Active Low.
Low current consumption:
o
< 1.2mA @ 27MHz
o
< 5µA when PDB is activated
Single 1.8V to 3.3V, ± 10% power supply
Operating temperature range from -40°C to 85°C
Available in 6-pin DFN, SOT23, and SC70
GREEN/RoHS compliant packages.
DESCRIPTION
The PL611s-28 consumes very low-power while
producing high performance clock outputs of up to
125MHz. Designed for low-power applications with
very stringent space requirement, PL611s-28
consumes about 1.2mA, while producing 2 distinct
outputs of 27MHz and 13.5MHz. Designed to fit in a
small SOT23, SC70, or DFN package for high
performance applications, the PL611s-28 offers the
best phase noise and jitter performance, and power
consumption of its rivals. The power down feature of
PL611s-28, when activated, allows the IC to
consume less than 5µA of power, while its
programming flexibility allows generating any output,
using a low-cost crystal or reference input. In
addition, one programmable I/O pin can be
configured as Output Enable (OE), Frequency
switching (FSEL), Power Down (PDB) input, or CLK1
(F
OUT
, F
REF
, F
REF
/2) output.
PACKAGE PIN CONFIGURATION
GND
PL611s-28
PL611s-28
PL611s-28
1
2
3
6
5
4
CLK0
VDD
OE, PDB,
FSEL, CLK1
GND
XIN, FIN
1
2
3
6
5
4
CLK0
VDD
XOUT
PL611s-28
PL611s-28
PL611s-28
PL611s-28
PL611s-28
PL611s-28
PL611s-28
PL611s-28
XIN, FIN
OE, PDB, FSEL, CLK1
GND
1
2
3
6
5
4
XOUT
VDD
CLK0
OE, PDB,
FSEL, CLK1
XIN, FIN
XOUT
SOT23-
SOT23-6L
23
35mm
mm)
(3.0 x 3.0 x 1.35mm)
DFN-
DFN-6L
mm)
(2.0 x 1.3 x 0.6mm)
SC70-
SC70-6L
70
mm)
(2.3 x 2.25 x 1.0mm)
BLOCK DIAGRAM
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 02/08/10 Page 1

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Reach Compliance Code unknown unknown unknown
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