MSM7717-01GS-K datasheet, PDF - EEWORLD Datasheet

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MSM7717-01GS-K: DescriptionPCM Codec, A/MU-Law, 1-Func, CMOS, PDSO24, 0.430 INCH, 1.27 MM PITCH, PLASTIC, SOP-24; CategoryWireless rf/communication Telecom circuit; File Size147KB，19 Pages; ManufacturerOKI; Websitehttp://www.oki.com

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MSM7717-01GS-K Overview

PCM Codec, A/MU-Law, 1-Func, CMOS, PDSO24, 0.430 INCH, 1.27 MM PITCH, PLASTIC, SOP-24

MSM7717-01GS-K Parametric

Parameter Name	Attribute value
Parts packaging code	SOIC
package instruction	SOP,
Contacts	24
Reach Compliance Code	unknown
Law of compression and extension	A/MU-LAW
filter	YES
JESD-30 code	R-PDSO-G24
length	15.95 mm
Number of functions	1
Number of terminals	24
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-30 °C
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Certification status	Not Qualified
Maximum seat height	2.5 mm
Nominal supply voltage	3 V
surface mount	YES
technology	CMOS
Telecom integrated circuit types	PCM CODEC
Temperature level	OTHER
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
width	7.9 mm
Base Number Matches	1

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E2U0041-28-81

¡ Semiconductor

MSM7717-01/02/03

¡ Semiconductor

Single Rail CODEC

This version: Aug. 1998

MSM7717-01/02/03

Previous version: Nov. 1996

GENERAL DESCRIPTION

The MSM7717 is a single-channel CODEC CMOS IC for voice signals ranging from 300 to 3400

Hz with filters for A/D and D/A conversion.

Designed especially for a single-power supply and low-power applications, the device is

optimized for ISDN terminals and telephone terminals in digital wireless systems.

The device uses the same transmission clocks as those used in the MSM7508B and MSM7509B.

The analog output, which can drive a 1.2 kW load, can directly drive a handset receiver

differentially.

FEATURES

• Single power supply: 2.7 V to 3.8 V

• Low power consumption

Operating mode:

20 mW Typ. V

= 3 V

Power-down mode:

0.03 mW Typ. V

= 3 V

• Conforms to ITU-T Companding law

MSM7717-01:

m/A-law

pin selectable

MSM7717-02:

m-law

MSM7717-03: A-law

• Built-in PLL eliminates a master clock

• Serial data rate: 64/128/256/512/1024 kHz

96/192/384/768/1536/1544/2048/200 kHz

• Adjustable transmit gain

• Adjustable receive gain

• Built-in reference voltage supply

• Package options:

24-pin plastic SOP (SOP24-P-430-1.27-K)

(Product name: MSM7717-01GS-K)

(Product name: MSM7717-02GS-K)

(Product name: MSM7717-03GS-K)

20-pin plastic SSOP (SSOP20-P-250-0.95-K) (Product name: MSM7717-01MS-K)

(Product name: MSM7717-02MS-K)

(Product name: MSM7717-03MS-K)

1/19

¡ Semiconductor

PWI, AOUT+, AOUT–

MSM7717-01/02/03

PWI is connected to the inverting input of the receive driver.

The receive driver output is connected to the AOUT– pin. Therefore, the receive level can be

adjusted with the pins VFRO, PWI, and AOUT–. When the PWI pin is not used, the PWI pin to

the AOUT– pin, and leave the pins AOUT– and AOUT+ open. The output of AOUT+ is inverted

with respect to the output of AOUT–. Since these outputs provide differential drive of an

impedance of 1.2 kW, these outputs can directly be connected to a receiver of handset using a

piezoelectric earphone. Refer to the application example. Since the driver amplifiers are being

activated during the power-saving mode, the amplifiers can output other external signals from

AOUT+ and AOUT– pins. AOUT+ and AOUT– outputs are in a high impedance state during

the power-down mode.

Gain = VO/VI = R7/R6

Analog output

VO ZL

–

AOUT+

Analog inverted output

ZL > 1.2 kW

R6 > 20 kW

External Signal Input

Receive filter

–

VFRO

PWI

AOUT–

Power supply for 2.7 V to 3.8 V. (Typically 3.0 V)

PCMIN

PCM data input.

A serial PCM data input to this pin is converted to an analog signal in synchronization with the

RSYNC signal and BCLK signal.

The data rate of PCM is equal to the frequency of the BCLK signal.

PCM signal is shifted in at a falling edge of the BCLK signal and latched into the internal register

when shifted by eight bits.

The start of the PCM data (MSD) is identified at the rising edge of RSYNC.

BCLK

Shift clock signal input for the PCMIN and PCMOUT signal.

The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, or 2048

kHz. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power

saving state.

The power-saving state means that the reference voltage generator (VRGEN), PLL, and receive

driver amplifiers are in the operating mode and the other circuits are in the non-operating mode.

5/19

MSM7717-01GS-K Related Products

	MSM7717-01GS-K	MSM7717-03MS-K	MSM7717-02MS-K	MSM7717-01MS-K	MSM7717-02GS-K	MSM7717-03GS-K
Description	PCM Codec, A/MU-Law, 1-Func, CMOS, PDSO24, 0.430 INCH, 1.27 MM PITCH, PLASTIC, SOP-24	PCM Codec, A-Law, 1-Func, CMOS, PDSO20, 0.250 INCH, 0.95 MM PITCH, PLASTIC, SSOP-20	PCM Codec, MU-Law, 1-Func, CMOS, PDSO20, 0.250 INCH, 0.95 MM PITCH, PLASTIC, SSOP-20	PCM Codec, A/MU-Law, 1-Func, CMOS, PDSO20, 0.250 INCH, 0.95 MM PITCH, PLASTIC, SSOP-20	PCM Codec, MU-Law, 1-Func, CMOS, PDSO24, 0.430 INCH, 1.27 MM PITCH, PLASTIC, SOP-24	PCM Codec, A-Law, 1-Func, CMOS, PDSO24, 0.430 INCH, 1.27 MM PITCH, PLASTIC, SOP-24
Parts packaging code	SOIC	SSOP	SSOP	SSOP	SOIC	SOIC
package instruction	SOP,	SSOP,	SSOP,	SSOP,	SOP,	SOP,
Contacts	24	20	20	20	24	24
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown
Law of compression and extension	A/MU-LAW	A-LAW	MU-LAW	A/MU-LAW	MU-LAW	A-LAW
filter	YES	YES	YES	YES	YES	YES
JESD-30 code	R-PDSO-G24	R-PDSO-G20	R-PDSO-G20	R-PDSO-G20	R-PDSO-G24	R-PDSO-G24
length	15.95 mm	10 mm	10 mm	10 mm	15.95 mm	15.95 mm
Number of functions	1	1	1	1	1	1
Number of terminals	24	20	20	20	24	24
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-30 °C	-30 °C	-30 °C	-30 °C	-30 °C	-30 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	SSOP	SSOP	SSOP	SOP	SOP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE	SMALL OUTLINE
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	2.5 mm	2 mm	2 mm	2 mm	2.5 mm	2.5 mm
Nominal supply voltage	3 V	3 V	3 V	3 V	3 V	3 V
surface mount	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Telecom integrated circuit types	PCM CODEC	PCM CODEC	PCM CODEC	PCM CODEC	PCM CODEC	PCM CODEC
Temperature level	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	1.27 mm	0.95 mm	0.95 mm	0.95 mm	1.27 mm	1.27 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
width	7.9 mm	5 mm	5 mm	5 mm	7.9 mm	7.9 mm
Base Number Matches	1	1	1	1	1	1

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