Section I. HardCopy Stratix
Device Family Data Sheet
This section provides designers with the data sheet specifications for
HardCopy
®
Stratix structured ASICs. The chapters contain feature
definitions of the internal architecture, JTAG boundary-scan testing
information, DC operating conditions, AC timing parameters, and a
reference to power consumption for HardCopy Stratix structured ASICs.
This section contains the following:
■
■
■
■
■
■
Chapter 1, Introduction to HardCopy Stratix Devices
Chapter 2, Description, Architecture, and Features
Chapter 3, Boundary-Scan Support
Chapter 4, Operating Conditions
Chapter 5, Quartus II Support for HardCopy Stratix Devices
Chapter 6, Design Guidelines for HardCopy Stratix Performance
Improvement
Revision History
Refer to each chapter for its own specific revision history. For information
on when each chapter was updated, refer to the Chapter Revision Dates
section, which appears in the complete handbook.
Altera Corporation
Section I–1
Preliminary
Revision History
HardCopy Series Handbook, Volume 1
Section I–2
Preliminary
Altera Corporation
1. Introduction to HardCopy
Stratix Devices
H51001-2.4
Introduction
HardCopy
®
Stratix
®
structured ASICs, Altera’s second-generation
HardCopy structured ASICs, are low-cost, high-performance devices
with the same architecture as the high-density Stratix FPGAs. The
combination of Stratix FPGAs for prototyping and design verification,
HardCopy Stratix devices for high-volume production, and the
Quartus
®
II design software beginning with version 3.0, provide a
complete and powerful alternative to ASIC design and development.
HardCopy Stratix devices are architecturally equivalent and have the
same features as the corresponding Stratix FPGA. They offer pin-to-pin
compatibility using the same package as the corresponding Stratix FPGA
prototype. Designers can prototype their design to verify functionality
with Stratix FPGAs before seamlessly migrating the proven design to a
HardCopy Stratix structured ASIC.
The Quartus II software provides a complete set of inexpensive and
easy-to-use tools for designing HardCopy Stratix devices. Using the
successful and proven methodology from HardCopy APEX™ devices,
Stratix FPGA designs can be seamlessly and quickly migrated to a
low-cost ASIC alternative. Designers can use the Quartus II software to
design HardCopy Stratix devices to obtain an average of 50% higher
performance and up to 40% lower power consumption than can be
achieved in the corresponding Stratix FPGAs. The migration process is
fully automated, requires minimal customer involvement, and takes
approximately eight weeks to deliver fully tested HardCopy Stratix
prototypes.
The HardCopy Stratix devices use the same base arrays across multiple
designs for a given device density and are customized using the top two
metal layers. The HardCopy Stratix family consists of the HC1S25,
HC1S30, HC1S40, HC1S60, and HC1S80 devices.
Table 1–1
provides the
details of the HardCopy Stratix devices.
Altera Corporation
September 2008
1–1
Preliminary
HardCopy Series Handbook, Volume 1
Table 1–1. HardCopy Stratix Devices and Features
Device
HC1S25
HC1S30
HC1S40
HC1S60
HC1S80
Notes to
Table 1–1:
(1)
(2)
(3)
(4)
LE: logic elements.
DSP: digital signal processing.
PLLs: phase-locked loops.
In HC1S30, HC1S40, and HC1S80 devices, there are fewer M-RAM blocks than in the equivalent Stratix FPGA. All
other resources are identical to the Stratix counterpart.
LEs
(1)
25,660
32,470
41,250
57,120
79,040
M512 Blocks
224
295
384
574
767
M4K Blocks
138
171
183
292
364
M-RAM
Blocks
2
2
(4)
2
(4)
6
6
(4)
DSP Blocks
(2)
10
12
14
18
22
PLLs
(3)
6
6
6
12
12
Features
HardCopy Stratix devices are manufactured on the same 1.5-V, 0.13
μm
all-layer-copper metal fabrication process (up to eight layers of metal) as
the Stratix FPGAs.
■
■
■
■
■
■
■
■
■
■
■
■
Preserves the functionality of a configured Stratix device
Pin-compatible with the Stratix counterparts
On average, 50% faster than their Stratix equivalents
On average, 40% less power consumption than their Stratix
equivalents
25,660 to 79,040 LEs
Up to 5,658,408 RAM bits available
TriMatrix memory architecture consisting of three RAM block sizes
to implement true dual-port memory and first-in-first-out (FIFO)
buffers
Embedded high-speed DSP blocks provide dedicated
implementation of multipliers, multiply-accumulate functions, and
finite impulse response (FIR) filters
Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per device
which provide identical features as the FPGA counterparts,
including spread spectrum, programmable bandwidth, clock
switchover, real-time PLL reconfiguration, advanced multiplication,
and phase shifting
Supports numerous single-ended and differential I/O standards
Supports high-speed networking and communications bus
standards including RapidIO™, UTOPIA IV, CSIX, HyperTransport
technology, 10G Ethernet XSBI, SPI-4 Phase 2 (POS-PHY Level 4),
and SFI-4
Differential on-chip termination support for LVDS
1–2
Preliminary
Altera Corporation
September 2008
Features
■
■
■
■
■
Supports high-speed external memory, including zero bus
turnaround (ZBT) SRAM, quad data rate (QDR and QDRII) SRAM,
double data rate (DDR) SDRAM, DDR fast-cycle RAM (FCRAM),
and single data rate (SDR) SDRAM
Support for multiple intellectual property (IP) megafunctions from
Altera
®
MegaCore
®
functions, and Altera Megafunction Partners
Program (AMPP
SM
) megafunctions
Available in space-saving flip-chip FineLine BGA
®
and wire-bond
packages (Tables
1–2
and
1–3)
Optional emulation of original FPGA configuration sequence
Optional instant-on power-up
The actual performance and power consumption improvements
over the Stratix equivalents mentioned in this data sheet are
design-dependent.
1
Table 1–2. HardCopy Stratix Device Package Options and I/O Pin Counts
Note (1)
Device
HC1S25
HC1S30
HC1S40
HC1S60
HC1S80
Notes to
Table 1–2:
(1)
(2)
(3)
(4)
Quartus II I/O pin counts include one additional pin,
PLLENA,
which is not a
general-purpose I/O pin.
PLLENA
can only be used to enable the PLLs.
This device uses a wire-bond package.
This device uses a flip-chip package.
In the Stratix EP1S40F780 FPGA, the I/O pins
U12
and
U18
are general-purpose
I/O pins. In the FPGA prototype,
EP1S40F780_HARDCOPY_FPGA_PROTOTYPE, and in the HardCopy Stratix
HC1S40F780 device,
U12
and
U18
must be connected to ground. The
EP1S40F780_HARDCOPY_FPGA_PROTOTYPE and HC1S40F780 pin-outs are
identical.
672-Pin
FineLine BGA
(2)
473
780-Pin
FineLine BGA
(3)
597
613
(4)
1,020-Pin
FineLine BGA
(3)
782
782
Altera Corporation
September 2008
1–3
Preliminary
京公网安备 11010802033920号
EEWORLD
