X28HC256
256k, 32k x 8-Bit
Data Sheet
September 21, 2011
FN8108.3
5V, Byte Alterable EEPROM
The X28HC256 is a second generation high performance
CMOS 32k x 8 EEPROM. It is fabricated with Intersil’s
proprietary, textured poly floating gate technology, providing
a highly reliable 5V only nonvolatile memory.
The X28HC256 supports a 128-byte page write operation,
effectively providing a 24µs/byte write cycle, and enabling
the entire memory to be typically rewritten in less than 0.8
seconds. The X28HC256 also features DATA Polling and
Toggle Bit Polling, two methods of providing early end of
write detection. The X28HC256 also supports the JEDEC
standard Software Data Protection feature for protecting
against inadvertent writes during power-up and power-down.
Endurance for the X28HC256 is specified as a minimum
1,000,000 write cycles per byte and an inherent data
retention of 100 years.
Features
• Access time: 70ns
• Simple byte and page write
- Single 5V supply
- No external high voltages or V
P-P
control circuits
- Self-timed
- No erase before write
- No complex programming algorithms
- No overerase problem
• Low power CMOS
- Active: 60mA
- Standby: 500µA
• Software data protection
- Protects data against system level inadvertent writes
• High speed page write capability
• Highly reliable Direct Write
™
cell
- Endurance: 1,000,000 cycles
- Data retention: 100 years
• Early end of write detection
- DATA polling
- Toggle bit polling
• Pb-free available (RoHS compliant)
Block Diagram
X BUFFERS
LATCHES AND
DECODER
A
0
TO A
14
ADDRESS
INPUTS
Y BUFFERS
LATCHES AND
DECODER
I/O BUFFERS
AND LATCHES
256kBIT
EEPROM
ARRAY
I/O
0
TO I/O
7
CE
OE
WE
V
CC
V
SS
CONTROL
LOGIC AND
TIMING
DATA INPUTS/OUTPUTS
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Copyright Intersil Americas Inc. 2005-2007, 2010, 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
X28HC256
Ordering Information
PART NUMBER
X28HC256J-15*
X28HC256JZ-15* (Note)
X28HC256JI-15*, **
X28HC256JIZ-15* (Note)
X28HC256P-15****
PART MARKING
X28HC256J-15 HY
X28HC256J-15 ZHY
X28HC256JI-15 HY
X28HC256JI-15 ZHY
X28HC256P-15 HY
ACCESS TIME
(ns)
TEMP. RANGE
(°C)
0 to +70
0 to +70
-40 to +85
-40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
-40 to +85
-40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
120
0 to +70
0 to +70
-40 to +85
-40 to +85
0 to +70
-40 to +85
-40 to +85
90
0 to +70
0 to +70
-40 to +85
0 to +70
-40 to +85
-40 to +85
32 Ld PLCC
32 Ld PLCC (Pb-free)
32 Ld PLCC
32 Ld PLCC (Pb-free)
28 Ld PDIP
28 Ld PDIP (Pb-free)
28 Ld PDIP
28 Ld PDIP (Pb-free)
28 Ld SOIC (300 mil)
28 Ld SOIC (300 mil) (Pb-free)
32 Ld PLCC
32 Ld PLCC (Pb-free)
32 Ld PLCC
32 Ld PLCC (Pb-free)
28 Ld PDIP
28 Ld PDIP (Pb-free)
28 Ld PDIP
28 Ld PDIP (Pb-free)
28 Ld SOIC (300 mils)
28 Ld SOIC (300 mils) (Pb-free)
28 Ld SOIC (300 mils)
28 Ld SOIC (300 mils) (Pb-free)
32 Ld PLCC (Pb-free)
32 Ld PLCC
32 Ld PLCC (Pb-free)
28 Ld PDIP
28 Ld PDIP (Pb-free)
28 Ld PDIP (Pb-free)
28 Ld SOIC (300 mils)
28 Ld SOIC (300 mils)
28 Ld SOIC (300 mils) (Pb-free)
PACKAGE
PKG. DWG. #
N32.45x55
N32.45x55
N32.45x55
N32.45x55
E28.6
E28.6
E28.6
E28.6
MDP0027
MDP0027
N32.45x55
N32.45x55
N32.45x55
N32.45x55
E28.6
E28.6
E28.6
E28.6
MDP0027
MDP0027
MDP0027
MDP0027
N32.45x55
N32.45x55
N32.45x55
E28.6
E28.6
E28.6
MDP0027
MDP0027
MDP0027
X28HC256PZ-15*** (Note) X28HC256P-15 HYZ
X28HC256PI-15****
X28HC256PI-15 HY
X28HC256PIZ-15*** (Note) X28HC256PI-15 HYZ
X28HC256SI-15*
X28HC256SIZ-15 (Note)
X28HC256J-12*
X28HC256JZ-12* (Note)
X28HC256JI-12*
X28HC256JIZ-12* (Note)
X28HC256P-12****
X28HC256SI-15 HY
X28HC256SI-15 HYZ
X28HC256J-12 HY
X28HC256J-12 ZHY
X28HC256JI-12 HY
X28HC256JI-12 ZHY
X28HC256P-12 HY
X28HC256PZ-12*** (Note) X28HC256P-12 HYZ
X28HC256PI-12****
X28HC256PI-12 HY
X28HC256PIZ-12*** (Note) X28HC256PI-12 HYZ
X28HC256S-12
X28HC256SZ-12 (Note)
X28HC256SI-12
X28HC256SIZ-12 (Note)
X28HC256JZ-90* (Note)
X28HC256JI-90*
X28HC256JIZ-90* (Note)
X28HC256P-90****
X28HC256S-12 HY
X28HC256S-12 HYZ
X28HC256SI-12 HY
X28HC256SI-12 HYZ
X28HC256J-90 ZHY
X28HC256JI-90 HY
X28HC256JI-90 ZHY
X28HC256P-90 HY
X28HC256PZ-90*** (Note) X28HC256P-90 HYZ
X28HC256PIZ-90 (Note)
X28HC256S-90
X28HC256SI-90
X28HC256SIZ-90 (Note)
X28HC256PI-90 HYZ
X28HC256S-90 HY
X28HC256SI-90 HY
X28HC256SI-90 HYZ
*Add "T1" suffix for tape and reel.
**Add "T2" suffix for tape and reel.
***Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
****Part at Prenotification (will become obsolete).
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2
FN8108.3
September 21, 2011
X28HC256
Pinouts
X28HC256
(28 LD FLATPACK, PDIP, SOIC)
TOP VIEW
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
V
SS
1
2
3
4
5
6
7
9
10
11
12
13
14
28
27
26
25
24
23
V
CC
WE
A
13
A
8
A
9
A
11
OE
A
10
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
X28HC256
(32 LD PLCC, LCC)
TOP VIEW
V
CC
WE
A
12
A
14
NC
A
13
29
28
27
X28HC256
26
25
24
23
A
8
A
9
A
11
NC
OE
A
10
CE
I/O
7
I/O
6
I/O
5
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
NC
I/O
0
5
6
7
8
9
10
11
I/O
1
4 3
2 1 32 31 30
22
X28HC256
8
21
20
19
18
17
16
15
12
22
13
21
14 15 16 17 18 19 20
I/O
2
V
SS
NC
I/O
3
I/O
4
Pin Descriptions
Addresses (A
0
to A
14
)
The Address inputs select an 8-bit memory location during a
read or write operation.
Pin Names
SYMBOL
A
0
to A
14
I/O
0
to I/O
7
WE
CE
OE
V
CC
V
SS
NC
DESCRIPTION
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
+5V
Ground
No Connect
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/write
operations. When CE is HIGH, power consumption is
reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers,
and is used to initiate read operations.
Data In/Data Out (I/O
0
to I/O
7
)
Data is written to or read from the X28HC256 through the I/O
pins.
Device Operation
Read
Read operations are initiated by both OE and CE LOW. The
read operation is terminated by either CE or OE returning
HIGH. This two line control architecture eliminates bus
contention in a system environment. The data bus will be in
a high impedance state when either OE or CE is HIGH.
Write Enable (WE)
The Write Enable input controls the writing of data to the
X28HC256.
Write
Write operations are initiated when both CE and WE are
LOW and OE is HIGH. The X28HC256 supports both a CE
and WE controlled write cycle. That is, the address is latched
by the falling edge of either CE or WE, whichever occurs
last. Similarly, the data is latched internally by the rising edge
of either CE or WE, whichever occurs first. A byte write
operation, once initiated, will automatically continue to
completion, typically within 3ms.
3
FN8108.3
September 21, 2011
X28HC256
Page Write Operation
The page write feature of the X28HC256 allows the entire
memory to be written in typically 0.8 seconds. Page write
allows up to one hundred twenty-eight bytes of data to be
consecutively written to the X28HC256, prior to the
commencement of the internal programming cycle. The host
can fetch data from another device within the system during
a page write operation (change the source address), but the
page address (A
7
through A
14
) for each subsequent valid
write cycle to the part during this operation must be the same
as the initial page address.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host can
write an additional one to one hundred twenty-seven bytes in
the same manner as the first byte was written. Each
successive byte load cycle, started by the WE HIGH to LOW
transition, must begin within 100µs of the falling edge of the
preceding WE. If a subsequent WE HIGH to LOW transition
is not detected within 100µs, the internal automatic
programming cycle will commence. There is no page write
window limitation. Effectively the page write window is
infinitely wide, so long as the host continues to access the
device within the byte load cycle time of 100µs.
cease, and the device will be accessible for additional read
and write operations.
DATA Polling I/O
DATA Polling can effectively halve the time for writing to the
X28HC256. The timing diagram in Figure 2 illustrates the
sequence of events on the bus. The software flow diagram in
Figure 3 illustrates one method of implementing the routine.
The Toggle Bit I/O
The Toggle Bit can eliminate the chore of saving and fetching
the last address and data in order to implement DATA Polling.
This can be especially helpful in an array comprised of
multiple X28HC256 memories that is frequently updated.
The timing diagram in Figure 4 illustrates the sequence of
events on the bus. The software flow diagram in Figure 5
illustrates a method for polling the Toggle Bit.
Hardware Data Protection
The X28HC256 provides two hardware features that protect
nonvolatile data from inadvertent writes.
• Default V
CC
Sense—All write functions are inhibited when
V
CC
is 3.5V typically.
Write Inhibit—Holding either OE LOW, WE HIGH, or CE
HIGH will prevent an inadvertent write cycle during power-up
and power-down, maintaining data integrity.
Write Operation Status Bits
The X28HC256 provides the user two write operation status
bits. These can be used to optimize a system write cycle
time. The status bits are mapped onto the I/O bus as shown
in Figure 1.
I/O
DP
TB
5
4
3
2
1
0
RESERVED
TOGGLE BIT
DATA POLLING
FIGURE 1. STATUS BIT ASSIGNMENT
DATA Polling (I/O
7
)
The X28HC256 features DATA Polling as a method to indicate
to the host system that the byte write or page write cycle has
completed. DATA Polling allows a simple bit test operation to
determine the status of the X28HC256. This eliminates
additional interrupt inputs or external hardware. During the
internal programming cycle, any attempt to read the last byte
written will produce the complement of that data on I/O
7
(i.e.,
write data = 0xxx xxxx, read data = 1xxx xxxx). Once the
programming cycle is complete, I/O
7
will reflect true data.
Toggle Bit (I/O
6
)
The X28HC256 also provides another method for
determining when the internal write cycle is complete. During
the internal programming cycle I/O
6
will toggle from HIGH to
LOW and LOW to HIGH on subsequent attempts to read the
device. When the internal cycle is complete the toggling will
4
FN8108.3
September 21, 2011
X28HC256
LAST
WRITE
WE
CE
OE
V
IH
I/O
7
HIGH Z
V
OL
V
OH
X28HC256
READY
An
An
An
An
A
0
TO A
14
An
An
An
FIGURE 2. DATA POLLING BUS SEQUENCE
WRITE DATA
WRITES
COMPLETE?
NO
YES
SAVE LAST DATA
AND ADDRESS
READ LAST
ADDRESS
IO
7
COMPARE?
YES
NO
X28HC256
READY
FIGURE 3. DATA POLLING SOFTWARE FLOW
5
FN8108.3
September 21, 2011
Embedded System
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