5962-0152203M2X datasheet, PDF

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5962-0152203M2X: DescriptionEE PLD, 20ns, CMOS, CDIP40, 0.600 INCH, CERDIP-40; CategoryProgrammable logic devices Programmable logic; File Size680KB，37 Pages; Manufacturere2v technologies

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5962-0152203M2X Overview

EE PLD, 20ns, CMOS, CDIP40, 0.600 INCH, CERDIP-40

5962-0152203M2X Parametric

Parameter Name	Attribute value
Parts packaging code	DIP
package instruction	0.600 INCH, CERDIP-40
Contacts	40
Reach Compliance Code	compliant
ECCN code	3A001.A.2.C
JESD-30 code	R-GDIP-T40
length	52.455 mm
Dedicated input times	14
Number of I/O lines	24
Number of terminals	40
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	14 DEDICATED INPUTS, 24 I/O
Output function	MACROCELL
Package body material	CERAMIC, GLASS-SEALED
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Programmable logic type	EE PLD
propagation delay	20 ns
Certification status	Not Qualified
Filter level	MIL-STD-883 Class B
Maximum seat height	5.72 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
width	15.24 mm
Base Number Matches	1

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Features

•

High-performance, High-density, Electrically-erasable Programmable Logic Device

Fully Connected Logic Array with 416 Product Terms

10 ns Maximum Pin-to-pin Delay for 5V Operation

Low-power Edge-sensing “L” Option with <1 mA Standby Current

24 Flexible Output Macrocells

– 48 Flip-flops – Two per Macrocell

– 72 Sum Terms

– All Flip-flops, I/O Pins Feed in Independently

D- or T-type Flip-flops

Product Term or Direct Input Pin Clocking

Registered or Combinatorial Internal Feedback

Backward Compatible with ATV2500B/BQL and ATV2500H/L Software

Advanced Electrically-erasable Technology

– Reprogrammable

– 100% Tested

44-lead Surface Mount Package

•

ATF2500C

CPLD Family

Datasheet

ATF2500C

ATF2500CL

ATF2500CQ

ATF2500CQL

Preliminary

Block Diagram

Description

The ATF2500C is the highest-density PLD available in a 44-pin package. With its fully

connected logic array and flexible macrocell structure, high gate utilization is easily

obtainable. The ATF2500C is a high-performance CMOS (electrically-erasable) pro-

grammable logic device (PLD) that utilizes Atmel’s proven electrically-erasable

technology.

Pin Configurations

Pin Name

CLK/IN

I/O

I/O 0,2,4...

I/O 1,3,5...

GND

VCC

Function

Logic Inputs

Pin Clock and Input

Bi-directional Buffers

“Even” I/O Buffers

“Odd” I/O Buffers

Ground

+5V Supply

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

VCC

I/O17

I/O16

I/O15

I/O14

I/O13

I/O12

DIP

I/O6

I/O7

I/O8

I/O9

I/O10

I/O11

GND

I/O23

I/O22

I/O21

I/O20

I/O19

I/O18

PLCC/LCC/JLCC

I/O1

I/O0

GND

CLK/IN

I/O6

I/O12

I/O18

I/O19

I/O2

I/O3

I/O4

I/O5

VCC

I/O17

I/O16

I/O15

I/O14

I/O13

I/O7

I/O8

I/O9

I/O10

I/O11

GND

I/O23

I/O22

I/O21

I/O20

Note:

For

ATF2500CQ

and

ATF2500CQL

(PLCC/LCC/JLCC packages) pin 4 and pin 26

GND connections are not required.

Rev. 0777G–12/01

The ATF2500C is organized around a single universal array. All pins and feedback terms are

always available to every macrocell. Each of the 38 logic pins are array inputs, as are the out-

puts of each flip-flop.

In the ATF2500C, four product terms are input to each sum term. Furthermore, each macro-

cell’s three sum terms can be combined to provide up to 12 product terms per sum term with

no performance penalty. Each flip-flop is individually selectable to be either D- or T-type, pro-

viding further logic compaction. Also, 24 of the flip-flops may be bypassed to provide internal

combinatorial feedback to the logic array.

Product terms provide individual clocks and asynchronous resets for each flip-flop. The flip-

flops may also be individually configured to have direct input pin clocking. Each output has its

own enable product term. Eight synchronous preset product terms serve local groups of either

four or eight flip-flops. Register preload functions are provided to simplify testing. All registers

automatically reset upon power-up.

The Atmel-unique “L” low-power feature is an edge-sensing option that is now field program-

mable for the ATF2500C family. The “L” feature utilizes Atmel-patented Input Transition

Detection (ITD) circuitry and is activated by selecting the “L” option from the program menu.

Using the

ATF2500C

Family’s Many

Advanced

Features

The ATF2500Cs advanced flexibility packs more usable gates into 44 leads than other PLDs.

Some of the ATF2500Cs key features are:

•

Fully Connected Logic Array –

Each array input is always available to every product

term. This makes logic placement a breeze.

Selectable D- and T-Type Registers –

Each ATF2500C flip-flop can be individually

configured as either D- or T-type. Using the T-type configuration, JK and SR flip-flops are

also easily created. These options allow more efficient product term usage.

Buried Combinatorial Feedback –

Each macrocell’s Q2 register may be bypassed to

feed its input (D/T2) directly back to the logic array. This provides further logic expansion

capability without using precious pin resources.

Selectable Synchronous/Asynchronous Clocking –

Each of the ATF2500Cs flip-flops

has a dedicated clock product term. This removes the constraint that all registers use the

same clock. Buried state machines, counters and registers can all coexist in one device

while running on separate clocks. Individual flip-flop clock source selection further allows

mixing higher performance pin clocking and flexible product term clocking within one

design.

A Total of 48 Registers –

The ATF2500C provides two flip-flops per macrocell – a total of

48. Each register has its own clock and reset terms, as well as its own sum term.

Independent I/O Pin and Feedback Paths –

Each I/O pin on the ATF2500C has a

dedicated input path. Each of the 48 registers has its own feedback term into the array as

well. These features, combined with individual product terms for each I/O’s output enable,

facilitate true bi-directional I/O design.

Combinable Sum Terms –

Each output macrocell’s three sum terms may be combined

into a single term. This provides a fan in of up to 12 product terms per sum term with

speed penalty.

•

ATF2500C Family

0777G–12/01

Preload and

Observability of

Registered

Outputs

The ATF2500Cs registers are provided with circuitry to allow loading of each register asyn-

chronously with either a high or a low. This feature will simplify testing since any state can be

forced into the registers to control test sequencing. A V

level on the odd I/O pins will force the

appropriate register high; a V

will force it low, independent of the polarity or other configura-

tion bit settings.

The PRELOAD state is entered by placing an 10.25V to 10.75V signal on SMP lead 42. When

the preload clock SMP lead 23 is pulsed high, the data on the I/O pins is placed into the 12

registers chosen by the Q select and even/odd select pins.

In this mode, the contents of the buried register bank will appear on the associated outputs

when the OE control signals are active.

Programming

Software

Support

All family members of the ATF2500C can be designed with Atmel-Synario

™

and Atmel-Win-

CUPL

™

. ProChip

™

designer support will be available Q102.

Additionally, the ATF2500C may be programmed to perform the ATV2500H/Ls functional sub-

set (no T-type flip-flops, pin clocking or D/T2 feedback) using the ATV2500H/L JEDEC file. In

this case, the ATF2500C becomes a direct replacement or speed upgrade for the

ATV2500H/L. The ATF2500CQ/CQL are direct replacements for the ATV2500BQ/BQL and

the AT2500H/L, including the lack of extra grounds on P4 and P26.

A single fuse is provided to prevent unauthorized copying of ATF2500C fuse patterns. Once

programmed, the outputs will read programmed during verify.

The security fuse should be programmed last, as its effect is immediate.

The security fuse also inhibits Preload and Q2 observability.

Security Fuse

Usage

Input and I/O

Pull-ups

All ATF2500C family members have programmable internal input and I/O pinkeeper circuits.

The default condition, including when using the AT2500CQ/CQL family to replace the

AT2500BQ/BQL or AT2500H/L, is that the pinkeepers are not activated.

When pinkeepers are active, inputs or I/Os not being driven externally will maintain their last

driven state. This ensures that all logic array inputs and device outputs are known states.

Pinkeepers are relatively weak active circuits that can be easily overridden by TTL-compatible

drivers (see input and I/O diagrams below).

ATF2500C Family

0777G–12/01

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