MT48LC16M8A2FB-6A datasheet, PDF

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MT48LC16M8A2FB-6A: DescriptionSynchronous DRAM, 16MX8, 5.4ns, CMOS, PBGA60,; Categorystorage storage; File Size4MB，74 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/

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MT48LC16M8A2FB-6A Overview

Synchronous DRAM, 16MX8, 5.4ns, CMOS, PBGA60,

MT48LC16M8A2FB-6A Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
package instruction	FBGA, BGA60,8X15,32
Reach Compliance Code	unknown
Maximum access time	5.4 ns
Maximum clock frequency (fCLK)	167 MHz
I/O type	COMMON
interleaved burst length	1,2,4,8
JESD-30 code	R-PBGA-B60
JESD-609 code	e0
memory density	134217728 bit
Memory IC Type	SYNCHRONOUS DRAM
memory width	8
Number of terminals	60
word count	16777216 words
character code	16000000
Maximum operating temperature	70 °C
Minimum operating temperature
organize	16MX8
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	FBGA
Encapsulate equivalent code	BGA60,8X15,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, FINE PITCH
power supply	3.3 V
Certification status	Not Qualified
refresh cycle	4096
Continuous burst length	1,2,4,8,FP
Maximum standby current	0.002 A
Maximum slew rate	0.33 mA
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Base Number Matches	1

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128Mb: x4, x8, x16 SDRAM

Features

SDRAM

MT48LC32M4A2 – 8 Meg x 4 x 4 banks

MT48LC16M8A2 – 4 Meg x 8 x 4 banks

MT48LC8M16A2 – 2 Meg x 16 x 4 banks

For the latest data sheet, please refer to the Micron Web site:

www.micron.com/dram

Features

• PC100-, and PC133-compliant

• Fully synchronous; all signals registered on positive edge

of system clock

• Internal pipelined operation; column address can be

changed every clock cycle

• Internal banks for hiding row access/precharge

• Programmable burst lengths: 1, 2, 4, 8, or full page

• Auto precharge, includes concurrent auto precharge, and

auto refresh modes

• Self refresh mode; standard and low power

• 64ms, 8,192-cycle refresh (15.625µs/row)

• LVTTL-compatible inputs and outputs

• Single +3.3 ±0.3V power supply

Figure 1:

54-Pin TSOP Pin Assignment

(Top View)

x16 x8 x4

x4 x8 x16

DQ0

DQ1

DQ1 DQ2

VssQ

DQ3

DQ2 DQ4

DQ5

DQ3 DQ6

VssQ

DQ7

NC DQML

WE#

CAS#

RAS#

CS#

BA0

BA1

A10

DQ1

Options

• Configurations

–

32 Meg x 4 (8 Meg x 4 x 4 banks)

–

16 Meg x 8 (4 Meg x 8 x 4 banks)

–

8 Meg x 16 (2 Meg x 16 x 4 banks)

• Write recovery (

WR)

–

WR = “2 CLK”

• Package/Pinout

–

Plastic package – OCPL

–

54-pin TSOP II (400 mil)

–

54-pin TSOP II (400 mil) Lead-free

–

60-ball FBGA (8mm x 16mm)

–

60-ball FBGA (8mm x 16mm)

Lead-free

–

54-ball VFBGA (8mm x 8mm)

–

54-ball VFBGA (8mm x 8mm)

Lead-free

• Timing (cycle time)

–

7.5ns @ CL = 3 (PC133)

–

7.5ns @ CL = 2 (PC133)

–

6.0ns @ CL = 3 (x16 only)

• Self refresh

–

Standard

–

Low power

• Design revision

• Operating temperature range

–

Commercial (0°C to +70°C)

–

Industrial (-40°C to +85°C)

Notes:

Designator

32M4

16M8

8M16

Notes:

Vss

DQ15 DQ7

VssQ

DQ14

DQ13 DQ6

DQ12

DQ11 DQ5

VssQ

DQ10

DQ9 DQ4

DQ8

Vss

DQMH DQM

CLK

CKE

A11

Vss

DQ3

DQ2

DQM

1. The # symbol indicates signal is active LOW. A dash (–) indicates

x8 and x4 pin function is same as x16 pin function.

Table 1:

Address Table

32 Meg x 4

16 Meg x 8

4 Meg x 8 x 4

banks

4K (A0–A11)

4 (BA0, BA1)

1K (A0–A9)

8 Meg x 16

2 Meg x 16 x 4

banks

4K (A0–A11)

4 (BA0, BA1)

512 (A0–A8)

8 Meg x 4 x 4

banks

4K (A0–A11)

4 (BA0, BA1)

2K (A0–A9,

A11)

Configuration

Refresh count

Row addressing

-75

-7E

-6A

None

Bank addressing

Column addressing

Table 2:

Key Timing Parameters

CL = CAS (Read) latency

Access Time

Speed

Grade

-6A

-7E

-75

Clock

Frequency

167 MHz

143 MHz

133 MHz

100 MHz

CL = 2

–

5.4ns

–

6ns

CL = 3

5.4ns

–

5.4ns

–

Setup

Time

1.5ns

Hold

Time

0.8ns

Refer to Micron Technical Note: TN-48-05.

Off-center parting line.

Consult Micron for availability.

x16 only.

PDF: 09005aef8091e66d/Source: 09005aef8091e625

128MSDRAM_1.fm - Rev. L 5/06 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

128Mb: x4, x8, x16 SDRAM

General Description

Table 3:

128Mb SDRAM Part Numbers

Part Number

MT48LC32M4A2TG

MT48LC32M4A2P

MT48LC16M8A2TG

MT48LC16M8A2P

MT48LC16M8A2FB

MT48LC16M8A2BB

MT48LC8M16A2TG

MT48LC8M16A2P

MT48LC8M16A2B4

MT48LC8M16A2F4

Notes:

Architecture

32 Meg x 4

16 Meg x 8

8 Meg x 16

1. FBGA Device Decode: http://www.micron.com/support/FBGA/FBGA.asp

General Description

The Micron

128Mb SDRAM is a high-speed CMOS, dynamic random-access memory

containing 134,217,728 bits. It is internally configured as a quad-bank DRAM with a

synchronous interface (all signals are registered on the positive edge of the clock signal,

CLK). Each of the x4’s 33,554,432-bit banks is organized as 4,096 rows by 2,048 columns

by 4 bits. Each of the x8’s 33,554,432-bit banks is organized as 4,096 rows by 1,024

columns by 8 bits. Each of the x16’s 33,554,432-bit banks is organized as 4,096 rows by

512 columns by 16 bits.

Read and write accesses to the SDRAM are burst oriented; accesses start at a selected

location and continue for a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an ACTIVE command, which is then

followed by a READ or WRITE command. The address bits registered coincident with the

ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select

the bank; A0–A11 select the row). The address bits registered coincident with the READ

or WRITE command are used to select the starting column location for the burst access.

The SDRAM provides for programmable read or write burst lengths of 1, 2, 4, or 8 loca-

tions, or the full page, with a burst terminate option. An auto precharge function may be

enabled to provide a self-timed row precharge that is initiated at the end of the burst

sequence.

The 128Mb SDRAM uses an internal pipelined architecture to achieve high-speed opera-

tion. This architecture is compatible with the 2n rule of prefetch architectures, but it also

allows the column address to be changed on every clock cycle to achieve a high-speed,

fully random access. Precharging one bank while accessing one of the other three banks

will hide the precharge cycles and provide seamless high-speed, random-access opera-

tion.

The 128Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh

mode is provided, along with a power-saving, power-down mode. All inputs and outputs

are LVTTL-compatible.

SDRAMs offer substantial advances in DRAM operating performance, including the

ability to synchronously burst data at a high data rate with automatic column-address

generation, the ability to interleave between internal banks in order to hide precharge

time and the capability to randomly change column addresses on each clock cycle

during a burst access.

PDF: 09005aef8091e66d/Source: 09005aef8091e625

128MSDRAM_1.fm - Rev. L 5/06 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

128Mb: x4, x8, x16 SDRAM

Table of Contents

Features 1

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

FBGA Ball Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Functional Block Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Ball/Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Mode Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Operating Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Write Burst Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

COMMAND INHIBIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

LOAD MODE REGISTER (LMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

ACTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

BURST TERMINATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Bank/row Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

WRITEs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Clock Suspend. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

BURST READ/SINGLE WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Concurrent Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

READ with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

WRITE with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Temperature and Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

PDF: 09005aef8091e66d/Source: 09005aef8091e625

128MSDRAMTOC.fm - Rev. L 5/06 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

128Mb: x4, x8, x16 SDRAM

List of Figures

54-Pin TSOP Pin Assignment (Top View) 1

Figure 2:

60-Ball FBGA Ball Assignment (Top View) 16 Meg x 8, 8mm x 16mm . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Figure 3:

54-Ball VFBGA Assignment (Top View) 8 Meg x 16, 8mm x 8mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Figure 4:

32 Meg x 4 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Figure 5:

16 Meg x 8 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Figure 6:

8 Meg x 16 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Figure 7:

Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Figure 8:

CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Figure 9:

Activating a Specific Row in a Specific Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Figure 10:

Example: Meeting

RCD (MIN) When 2 <

RCD (MIN)/

≤

3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Figure 11:

READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Figure 12:

CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Figure 13:

Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Figure 14:

Random READ Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Figure 15:

READ-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Figure 16:

READ-to-WRITE with Extra Clock Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Figure 17:

READ-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Figure 18:

Terminating a READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Figure 19:

WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 20:

WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 21:

WRITE-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 22:

Random WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 23:

WRITE-to-READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Figure 24:

WRITE-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Figure 25:

Terminating a WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Figure 26:

PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Figure 27:

Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Figure 28:

Clock Suspend During WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Figure 29:

Clock Suspend During READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Figure 30:

READ With Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Figure 31:

READ With Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Figure 32:

WRITE With Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Figure 33:

WRITE With Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Figure 34:

Example Temperature Test Point Location, 54-Pin TSOP: Top View . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Figure 35:

Example Temperature Test Point Location, 54-Ball VFBGA: Top View . . . . . . . . . . . . . . . . . . . . . . . . .47

Figure 36:

Example Temperature Test Point Location, 60-Ball FBGA: Top View . . . . . . . . . . . . . . . . . . . . . . . . . .47

Figure 37:

Initialize and Load Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Figure 38:

Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Figure 39:

Clock Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Figure 40:

Auto Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Figure 41:

Self Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Figure 42:

READ – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Figure 43:

READ – With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Figure 44:

Single READ – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Figure 45:

Single READ – With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Figure 46:

Alternating Bank Read Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Figure 47:

READ – Full-Page Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Figure 48:

READ – DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Figure 49:

WRITE – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Figure 50:

WRITE – With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Figure 51:

Single WRITE – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Figure 52:

Single WRITE – With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Figure 53:

Alternating Bank Write Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Figure 54:

WRITE – Full-page Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Figure 55:

WRITE – DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Figure 56:

54-Pin Plastic TSOP (400 mil) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

PDF: 09005aef8091e66d/Source: 09005aef8091e625

128MSDRAMLOF.fm - Rev. L 5/06 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT48LC16M8A2FB-6A Related Products

	MT48LC16M8A2FB-6A	MT48LC8M16A2B4-75LIT	MT48LC8M16A2F4-7ELIT
Description	Synchronous DRAM, 16MX8, 5.4ns, CMOS, PBGA60,	Synchronous DRAM, 8MX16, 5.4ns, CMOS, PBGA54	Synchronous DRAM, 8MX16, 5.4ns, CMOS, PBGA54,
Is it Rohs certified?	incompatible	conform to	incompatible
Reach Compliance Code	unknown	unknown	not_compliant
Maximum access time	5.4 ns	5.4 ns	5.4 ns
Maximum clock frequency (fCLK)	167 MHz	133 MHz	143 MHz
I/O type	COMMON	COMMON	COMMON
interleaved burst length	1,2,4,8	1,2,4,8	1,2,4,8
JESD-30 code	R-PBGA-B60	S-PBGA-B54	S-PBGA-B54
memory density	134217728 bit	134217728 bit	134217728 bit
Memory IC Type	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM
memory width	8	16	16
Number of terminals	60	54	54
word count	16777216 words	8388608 words	8388608 words
character code	16000000	8000000	8000000
Maximum operating temperature	70 °C	85 °C	85 °C
Minimum operating temperature	-	-40 °C	-40 °C
organize	16MX8	8MX16	8MX16
Output characteristics	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	FBGA	FBGA	FBGA
Encapsulate equivalent code	BGA60,8X15,32	BGA54,9X9,32	BGA54,9X9,32
Package shape	RECTANGULAR	SQUARE	SQUARE
Package form	GRID ARRAY, FINE PITCH	GRID ARRAY, FINE PITCH	GRID ARRAY, FINE PITCH
power supply	3.3 V	3.3 V	3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified
refresh cycle	4096	4096	4096
Continuous burst length	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP
Maximum standby current	0.002 A	0.002 A	0.002 A
Maximum slew rate	0.33 mA	0.31 mA	0.33 mA
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	BALL	BALL	BALL
Terminal pitch	0.8 mm	0.8 mm	0.8 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM
package instruction	FBGA, BGA60,8X15,32	FBGA, BGA54,9X9,32	-
JESD-609 code	e0	-	e0
Terminal surface	Tin/Lead (Sn/Pb)	-	Tin/Lead (Sn/Pb)
Maker	-	Micron Technology	Micron Technology

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