2. Ordering Information ..................................................................................................................................................... 4
6. Input/Output Function Description ................................................................................................................................ 10
7. Command Truth Table .................................................................................................................................................. 11
8. General Description ...................................................................................................................................................... 12
9. Absolute Maximum Rating ............................................................................................................................................ 12
10. DC Operating Conditions ............................................................................................................................................ 12
11. DDR SDRAM Spec Items & Test Conditions .............................................................................................................. 13
15. AC Operating Conditions ............................................................................................................................................ 17
16. AC Overshoot/Undershoot specification for Address and Control Pins ...................................................................... 17
17. Overshoot/Undershoot specification for Data, Strobe and Mask Pins ........................................................................ 18
18. AC Timing Parameters & Specifications ..................................................................................................................... 19
19. System Characteristics for DDR SDRAM ................................................................................................................... 20
21. System Notes.............................................................................................................................................................. 23
22. IBIS : I/V Characteristics for Input and Output Buffers................................................................................................ 24
-3-
K4H510438J
K4H510838J
K4H511638J
datasheet
Rev. 1.1
DDR SDRAM
1. Key Features
• V
DD
: 2.5V ± 0.2V, V
DDQ
: 2.5V ± 0.2V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
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