K9K4G08U1M
K9F2G08U0M K9F2G16U0M
FLASH MEMORY
Document Title
256M x 8 Bit / 128M x 16 Bit / 512M x 8 Bit NAND Flash Memory
Revision History
Revision No
0.0
0.1
History
1. Initial issue
1. Add the Rp vs tr ,tf & Rp vs Ibusy graph for 1.8V device (Page 34)
2. Add the data protection Vcc guidence for 1.8V device - below about
1.1V. (Page 35)
Draft Date
Sep. 19.2001
Nov. 22. 2002
Remark
Advance
Preliminary
0.2
The min. Vcc value 1.8V devices is changed.
K9F2GXXQ0M : Vcc 1.65V~1.95V --> 1.70V~1.95V
Mar. 6.2003
Preliminary
0.3
Few current value is changed.
Before
K9F2GXXQ0M
Typ.
I
SB
2
I
LI
I
LO
After
K9F2GXXQ0M
Typ.
I
SB
2
I
LI
I
LO
10
-
-
Max.
50
±10
±10
20
-
-
Max.
100
±20
±20
Typ.
20
-
-
Apr. 2. 2003
Unit : us
K9F2GXXU0M
Max.
100
±20
±20
Preliminary
K9F2GXXU0M
Typ.
10
-
-
Max.
50
±10
±10
Apr. 9. 2003
Preliminary
0.4
1. The 3rd Byte ID after 90h ID read command is don’t cared.
The 5th Byte ID after 90h ID read command is deleted.
2. Note is added.
(VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for
durations of 20 ns or less.)
3. Pb-free Package is added.
K9F2G08Q0M-PCB0,PIB0
K9F2G08U0M-PCB0,PIB0
K9F2G16U0M-PCB0,PIB0
K9F2G16Q0M-PCB0,PIB0
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near your office.
1
K9K4G08U1M
K9F2G08U0M K9F2G16U0M
FLASH MEMORY
Document Title
256M x 8 Bit / 128M x 16 Bit/ 512M x 8 Bit NAND Flash Memory
Revision History
Revision No
0.5
History
1. The value of AC parameters for K9F2G08U0M are changed.
ITEM
t
WC
t
WP
t
WH
t
RC
t
RP
t
REH
t
REA
t
CEA
t
ADL
K9F2G08U0M
Before
45
25
15
50
25
15
30
45
-
After
30
15
10
30
15
10
18
23
100
Draft Date
Apr. 22.2004
Remark
Preliminary
2. The definition and value of setup and hold time are changed.
ITEM
t
CLS
t
CLH
t
CS
t
CH
t
ALS
t
ALH
t
DS
t
DH
K9F2G16U0M
K9F2GXXQ0M
25
10
35
10
25
10
20
10
K9F2G08U0M
10
5
15
5
10
5
10
5
3. The tADL(Address to Data Loading Time) is added.
- tADL Minimum 100ns (Page 11, 22~25)
-
tADL is the time from the WE rising edge of final address cycle
to the WE rising edge of first data cycle at program operation.
4. Added addressing method for program operation
0.6
0.7
1. PKG(TSOP1, WSOP1) Dimension Change
1. Technical note is changed
2. Notes of the AC timing characteristics are added
3. The description of Copy-back program is changed
4. 52ULGA Package is added
May. 19. 2004
Jan. 21. 2005
Preliminary
Preliminary
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near your office.
2
K9K4G08U1M
K9F2G08U0M K9F2G16U0M
FLASH MEMORY
Document Title
256M x 8 Bit / 128M x 16 Bit/ 512M x 8 Bit NAND Flash Memory
Revision History
Revision No
0.8
0.9
History
1. CE access time : 23ns->35ns (p.13)
1. The value of tREA for 3.3V device is changed.(18ns->20ns)
2. EDO mode is added.
1. The flow chart to creat the initial invalid block table is changed.
Draft Date
Feb. 14. 2005
May 4
2005
Remark
Preliminary
1.0
May 6
2005
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near your office.
3
K9K4G08U1M
K9F2G08U0M K9F2G16U0M
FLASH MEMORY
256M x 8 Bit / 128M x 16 Bit/ 512M x 8 Bit NAND Flash Memory
PRODUCT LIST
Part Number
K9F2G08U0M-Y,P
K9F2G16U0M-Y,P
K9K4G08U1M-I
2.7 ~ 3.6V
Vcc Range
Organization
X8
X16
X8
52ULGA
PKG Type
TSOP1
FEATURES
•
Voltage Supply
-2.7 V ~3.6 V
•
Organization
- Memory Cell Array
-X8 device(K9F2G08X0M) : (256M + 8,192K)bit x 8bit
-X16 device(K9F2G16X0M) : (128M + 4,096K)bit x 16bit
- Data Register
-X8 device(K9F2G08X0M): (2K + 64)bit x8bit
-X16 device(K9F2G16X0M): (1K + 32)bit x16bit
- Cache Register
-X8 device(K9F2G08X0M) : (2K + 64)bit x8bit
-X16 device(K9F2G16X0M) : (1K + 32)bit x16bit
•
Automatic Program and Erase
- Page Program
-X8 device(K9F2G08X0M) : (2K + 64)Byte
-X16 device(K9F2G16X0M) : (1K + 32)Word
- Block Erase
-X8 device(K9F2G08X0M) : (128K + 4K)Byte
-X16 device(K9F2G16X0M) : (64K + 2K)Word
•
Page Read Operation
- Page Size
- X8 device(K9F2G08X0M) : 2K-Byte
- X16 device(K9F2G16X0M) : 1K-Word
- Random Read : 25µs(Max.)
- Serial Access : 30ns(Min.)
•
Fast Write Cycle Time
- Page Program time : 200µs(Typ.)
- Block Erase Time : 2ms(Typ.)
•
Command/Address/Data Multiplexed I/O Port
•
Hardware Data Protection
- Program/Erase Lockout During Power Transitions
•
Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
- Data Retention : 10 Years
•
Command Register Operation
•
Cache Program Operation for High Performance Program
•
Power-On Auto-Read Operation
•
Intelligent Copy-Back Operation
•
Unique ID for Copyright Protection
•
Package :
- K9F2GXXU0M-YCB0/YIB0
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
- K9F2GXXU0M-PCB0/PIB0 : Pb-FREE PACKAGE
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
- K9K4G08U1M-ICB0/IIB0
52 - Pin ULGA (12 x 17 / 0.65 mm pitch)
GENERAL DESCRIPTION
Offered in 256Mx8bit or 128Mx16bit, the K9F2GXXU0M is 2G bit with spare 64M bit capacity. Its NAND cell provides the most cost-
effective solution for the solid state mass storage market. A program operation can be performed in typical 200µs on the 2112-
byte(X8 device) or 1056-word(X16 device) page and an erase operation can be performed in typical 2ms on a 128K-byte(X8 device)
or 64K-word(X16 device) block. Data in the data page can be read out at 30ns cycle time per byte(X8 device) or word(X16 device)..
The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates
all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the
write-intensive systems can take advantage of the K9F2GXXU0M′s extended reliability of 100K program/erase cycles by providing
ECC(Error Correcting Code) with real time mapping-out algorithm. The K9F2GXXU0M is an optimum solution for large nonvolatile
storage applications such as solid state file storage and other portable applications requiring non-volatility.
4
K9K4G08U1M
K9F2G08U0M K9F2G16U0M
PIN CONFIGURATION (TSOP1)
K9F2GXXU0M-YCB0,PCB0/YIB0,PIB0
X16
N.C
N.C
N.C
N.C
N.C
N.C
R/B
RE
CE
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
FLASH MEMORY
X8
N.C
N.C
N.C
N.C
N.C
N.C
R/B
RE
CE
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
X8
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
PRE
Vcc
Vss
N.C
N.C
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
N.C
X16
Vss
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
N.C
PRE
Vcc
N.C
N.C
N.C
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
Vss
48-pin TSOP1
Standard Type
12mm x 20mm
PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220AF
Unit :mm/Inch
0.10
MAX
0.004
#48
( 0.25 )
0.010
12.40
0.488 MAX
#24
#25
1.00
±0.05
0.039
±0.002
0.25
0.010 TYP
+0.075
20.00
±0.20
0.787
±0.008
0.20
-0.03
+0.07
#1
0.008
-0.001
0.16
-0.03
+0.07
+0.003
0.50
0.0197
12.00
0.472
0.05
0.002 MIN
0.125
0.035
0~8°
0.45~0.75
0.018~0.030
( 0.50 )
0.020
5
0.005
-0.001
+0.003
18.40
±0.10
0.724
±0.004
1.20
0.047MAX
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