Ultra Low Power/High Speed CMOS SRAM
512K X 16 bit
Pb-Free and Green package materials are compliant to RoHS
BH616UV8011
FEATURES
Wide V
CC
low operation voltage : 1.65V ~ 3.6V
Ultra low power consumption :
Operation current : 12mA (Max.)at 55ns
V
CC
= 3.6V
2mA (Max.) at 1MHz
O
Standby current : 15uA (Max.) at 3.0V/85 C
O
Data retention current : 7uA (Max.) at 85 C
V
CC
= 1.2V
High speed access time :
-55/-70
55ns (Max.) at V
CC
=3V
70ns (Max.) at V
CC
=1.8V
Automatic power down when chip is deselected
Easy expansion with CE1, CE2 and OE options
I/O Configuration x8/x16 selectable by LB and UB pin.
Three state outputs and TTL compatible
Fully static operation, no clock, no refresh
Data retention supply voltage as low as 1.0V
DESCRIPTION
The BH616UV8011 is a high performance, ultra low power CMOS
Static Random Access Memory organized as 524,288 by 16 bits and
operates in a wide range of 1.65V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both
high speed and low power features with maximum standby current of
O
15uA at 3.6V at 85 C and maximum access time of 55ns/70ns at
3V/1.8V .
Easy memory expansion is provided by an active LOW chip enable
(CE1), an active HIGH chip enable (CE2) and active LOW output
enable (OE) and three-state output drivers.
The BH616UV8011 has an automatic power down feature, reducing
the power consumption significantly when chip is deselected.
The BH616UV8011 is available in DICE form, JEDEC standard
48-pin TSOP-I and 48-ball BGA package.
POWER CONSUMPTION
POWER DISSIPATION
PRODUCT
FAMILY
BH616UV8011DI
BH616UV8011AI
BH616UV8011TI
Industrial
O
O
-40 C to +85 C
15uA
12uA
2mA
6mA
12mA
1.5mA
5mA
8mA
OPERATING
TEMPERATURE
STANDBY
(I
CCSB1
, Max)
Operating
(I
CC
, Max)
PKG TYPE
V
CC
=1.8V
10MHz
f
Max.
V
CC
=3.6V
V
CC
=1.8V
1MHz
V
CC
=3.6V
10MHz
f
Max.
1MHz
DICE
BGA-48-0608
TSOP I-48
PIN CONFIGURATIONS
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
CE2
NC
UB
LB
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
NC
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
VSS
CE1
A0
BLOCK DIAGRAM
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
Address
Input
Buffer
10
Row
Decoder
1024
Memory Array
BH616UV8011TI
1024 x 8192
8192
DQ0
.
.
.
.
.
.
DQ15
CE2
CE1
WE
OE
UB
LB
V
CC
V
SS
.
.
.
.
.
.
16
16
Data
Input
Buffer
Data
Output
Buffer
16
512
Column Decoder
9
Address Input Buffer
Control
16
Column I/O
Write Driver
Sense Amp
1
A
B
C
D
E
F
G
H
LB
DQ8
DQ9
VSS
VCC
DQ14
DQ15
A18
2
OE
UB
DQ10
DQ11
DQ12
DQ13
NC
A8
3
A0
A3
A5
A17
NC
A14
A12
A9
4
A1
A4
A6
A7
A16
A15
A13
A10
5
A2
CE1
DQ1
DQ3
DQ4
DQ5
WE
A11
6
CE2
DQ0
DQ2
VCC
VSS
DQ6
DQ7
NC
A18 A17 A15 A14 A13 A16 A2 A1 A0
48-ball BGA top view
Brilliance Semiconductor, Inc.
reserves the right to change products and specifications without notice.
Detailed product characteristic test report is available upon request and being accepted.
R0201-BH616UV8011
1
Revision
1.2
Oct.
2008
BH616UV8011
PIN DESCRIPTIONS
Name
A0-A18 Address Input
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
WE Write Enable Input
Function
These 19 address inputs select one of the 524,288 x 16 bit in the RAM
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in standby power mode. The DQ pins will be in the high impedance
state when the device is deselected.
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impendence state when OE is inactive.
LB and UB Data Byte Control Input
DQ0-DQ15 Data Input/Output
Ports
V
CC
V
SS
Lower byte and upper byte data input/output control pins.
16 bi-directional ports are used to read data from or write data into the RAM.
Power Supply
Ground
TRUTH TABLE
MODE
Chip De-selected
(Power Down)
CE1
H
X
X
CE2
X
L
X
H
H
WE
X
X
X
H
H
OE
X
X
X
H
H
LB
X
X
H
L
X
L
UB
X
X
H
X
L
L
L
H
L
L
H
DQ0~DQ7 DQ8~DQ15 V
CC
CURRENT
High Z
High Z
High Z
High Z
High Z
D
OUT
High Z
D
OUT
D
IN
X
D
IN
High Z
High Z
High Z
High Z
High Z
D
OUT
D
OUT
High Z
D
IN
D
IN
X
I
CCSB
, I
CCSB1
I
CCSB
, I
CCSB1
I
CCSB
, I
CCSB1
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
Output Disabled
L
L
Read
L
H
H
L
H
L
L
Write
L
H
L
X
H
L
NOTES: H means V
IH
; L means V
IL
; X means don’t care (Must be V
IH
or V
IL
state)
R0201-BH616UV8011
2
Revision
1.2
Oct.
2008
BH616UV8011
ABSOLUTE MAXIMUM RATINGS
(1)
SYMBOL
V
TERM
T
BIAS
T
STG
P
T
I
OUT
OPERATING RANGE
UNITS
V
O
PARAMETER
Terminal Voltage with
Respect to GND
Temperature Under
Bias
Storage Temperature
Power Dissipation
DC Output Current
RATING
-0.5
(2)
RANG
Industrial
AMBIENT
TEMPERATURE
-40 C to + 85 C
O
O
V
CC
1.65V ~ 3.6V
to 4.6V
-40 to +125
-60 to +150
1.0
20
C
C
O
CAPACITANCE
(1)
(T
A
= 25
O
C, f = 1.0MHz)
SYMBOL PAMAMETER CONDITIONS MAX. UNITS
W
mA
C
IN
Input
Capacitance
Input/Output
Capacitance
V
IN
= 0V
V
I/O
= 0V
6
8
pF
pF
1. Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. –2.0V in case of AC pulse width less than 30 ns
C
IO
1. This parameter is guaranteed and not 100% tested.
DC ELECTRICAL CHARACTERISTICS (T
A
= -40
O
C to +85
O
C)
PARAMETER
NAME
V
CC
V
IL
V
IH
I
IL
I
LO
V
OL
V
OH
I
CC
I
CC1
I
CCSB
I
CCSB1
PARAMETER
Power Supply
V
CC
=1.8V
V
CC
=3.6V
TEST CONDITIONS
MIN.
1.65
(2)
TYP.
(1)
--
MAX.
3.6
0.4
0.6
V
CC
+0.3
(3)
UNITS
V
Input Low Voltage
-0.3
--
V
Input High Voltage
V
IN
= 0V to V
CC
,
CE1 = V
IH
or CE2 = V
IL
V
I/O
= 0V to V
CC
,
Output Leakage Current
V
CC
=1.8V
V
CC
=3.6V
1.4
2.2
--
--
V
Input Leakage Current
--
1
uA
CE1 = V
IH
or CE2 = V
IL
or OE = V
IH
or
UB = LB = V
IH
V
CC
= Max, I
OL
= 0.2mA
V
CC
= Max, I
OL
= 2.0mA
V
CC
= Min, I
OH
= -0.1mA
V
CC
= Min, I
OH
= -1.0mA
CE1 = V
IL
and CE2 = V
IH
,
I
DQ
= 0mA, f = F
MAX
(4)
--
--
1
0.2
0.4
--
8
12
1.5
2.0
0.5
1.0
12
15
uA
Output Low Voltage
V
CC
=1.8V
V
CC
=3.6V
V
CC
=1.8V
V
CC
=3.6V
V
CC
=1.8V
V
CC
=3.6V
V
CC
=1.8V
V
CC
=3.6V
V
CC
=1.8V
V
CC
=3.6V
V
CC
=1.8V
V
CC
=3.6V
--
V
CC
-0.2
2.4
--
--
V
Output High Voltage
Operating Power Supply
Current
Operating Power Supply
Current
Standby Current – TTL
--
6
8
1.0
1.5
--
2.0
2.5
(5)
V
mA
CE1 = V
IL
and CE2 = V
IH
,
I
DQ
= 0mA, f = 1MHz
CE1 = V
IH
, or CE2 = V
IL
,
I
DQ
= 0mA
CE1≧V
CC
-0.2V or CE2≦0.2V,
V
IN
≧V
CC
-0.2V or V
IN
≦0.2V
--
mA
--
mA
Standby Current – CMOS
O
--
uA
1. Typical characteristics are at T
A
=25 C and not 100% tested.
2. Undershoot: -1.0V in case of pulse width less than 20 ns.
3. Overshoot: V
CC
+1.0V in case of pulse width less than 20 ns.
4. F
MAX
=1/t
RC.
5. V
CC
=3.0V
R0201-BH616UV8011
3
Revision
1.2
Oct.
2008
BH616UV8011
DATA RETENTION CHARACTERISTICS (T
A
= -40
O
C to +85
O
C)
SYMBOL
V
DR
I
CCDR
t
CDR
t
R
PARAMETER
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
O
TEST CONDITIONS
CE1≧V
CC
-0.2V or CE2≦0.2V,
V
IN
≧V
CC
-0.2V or V
IN
≦0.2V
CE1≧V
CC
-0.2V or CE2≦0.2V,
V
IN
≧V
CC
-0.2V or V
IN
≦0.2V
V
CC
=1.2V
MIN.
1.0
--
0
TYP.
(1)
--
1.2
--
MAX.
--
7.0
--
--
UNITS
V
uA
ns
ns
See Retention Waveform
t
RC
(2)
--
1. Typical characteristics are at T
A
=25 C and not 100% tested.
2. t
RC
= Read Cycle Time.
LOW V
CC
DATA RETENTION WAVEFORM (1) (CE1 Controlled)
Data Retention Mode
V
CC
V
CC
V
DR
≧1.0V
V
CC
t
CDR
V
IH
CE1≧V
CC
- 0.2V
t
R
V
IH
CE1
LOW V
CC
DATA RETENTION WAVEFORM (2) (CE2 Controlled)
Data Retention Mode
V
CC
V
CC
V
DR
≧1.0V
V
CC
t
CDR
CE2≦0.2V
t
R
CE2
V
IL
V
IL
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing
Reference Level
t
CLZ1
, t
CLZ2
, t
BE
, t
OLZ
, t
CHZ1
,
t
CHZ2
, t
BDO
, t
OHZ
, t
WHZ
, t
OW
Output Load
Others
V
CC
/ 0V
1V/ns
0.5Vcc
C
L
= 5pF+1TTL
C
L
= 30pF+1TTL
ALL INPUT PULSES
1 TTL
Output
C
(1)
L
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
MUST BE
STEADY
MAY CHANGE
FROM “H” TO “L”
MAY CHANGE
FROM “L” TO “H”
DON’T CARE
ANY CHANGE
PERMITTED
DOES NOT
APPLY
OUTPUTS
MUST BE
STEADY
WILL BE CHANGE
FROM “H” TO “L”
WILL BE CHANGE
FROM “L” TO “H”
CHANGE :
STATE UNKNOW
CENTER LINE IS
HIGH INPEDANCE
“OFF” STATE
V
CC
GND
10%
90%
90%
10%
→ ←
Rise Time:
1V/ns
→ ←
Fall Time:
1V/ns
1. Including jig and scope capacitance.
R0201-BH616UV8011
4
Revision
1.2
Oct.
2008
BH616UV8011
AC ELECTRICAL CHARACTERISTICS (T
A
= -40
O
C to +85
O
C)
READ CYCLE
JEDEC
PARANETER
PARAMETER
NAME
NAME
CYCLE TIME : 55ns
(Vcc=3.0V)
MIN.
55
--
(CE1)
(CE2)
(LB, UB)
--
--
--
--
(CE1)
(CE2)
(LB, UB)
10
10
10
5
(CE1)
(CE2)
--
--
--
--
10
TYP.
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
MAX.
--
55
55
55
55
30
--
--
--
--
25
25
25
25
--
CYCLE TIME : 70ns
(Vcc=1.8V)
MIN.
70
--
--
--
--
--
10
10
10
5
--
--
--
--
10
TYP.
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
MAX.
--
70
70
70
70
35
--
--
--
--
30
30
30
30
--
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select Access Time
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output Low Z
Chip Select to Output High Z
Chip Select to Output High Z
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
AVAX
t
AVQX
t
E1LQV
t
E2LQV
t
BLQV
t
GLQV
t
E1LQX
t
E2LQX
t
BLQX
t
GLQX
t
E1HQZ
t
E2HQZ
t
BHQZ
t
GHQZ
t
AVQX
t
RC
t
AA
t
ACS1
t
ACS2
t
BA
t
OE
t
CLZ1
t
CLZ2
t
BE
t
OLZ
t
CHZ1
t
CHZ2
t
BDO
t
OHZ
t
OH
Data Byte Control to Output High Z (LB, UB)
Output Enable to Output High Z
Data Hold from Address Change
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE 1
(1,2,4)
t
RC
ADDRESS
t
OH
D
OUT
t
AA
t
OH
R0201-BH616UV8011
5
Revision
1.2
Oct.
2008
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