FBDIMM
DDR2 SDRAM
DDR2 Fully Buffered DIMM
240pin FBDIMMs based on 512Mb C-die
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure couldresult in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
1 of 31
Rev. 1.4 April 2007
FBDIMM
Table of Contents
DDR2 SDRAM
1.0 FEATURES .....................................................................................................................................4
2.0 FBDIMM GENERALS .....................................................................................................................5
2.1 FB-DIMM Operation Overview
.........................................................................................................5
2.2 FB-DIMM Channel Frequency Scaling
..............................................................................................6
2.3 FB-DIMM Clocking Scheme
............................................................................................................7
2.4 FB-DIMM Protocol
.........................................................................................................................7
2.5 Southbound Command Delivery
......................................................................................................8
2.6 Basic Timing Diagram
....................................................................................................................9
2.7 Advanced Memory Buffer Block Diagram
.......................................................................................11
2.8 Interfaces
...................................................................................................................................12
3.0 FBD HIGH-SPEED DIFFERENTIAL POINT TO POINT LINK (at 1.5 V) INTERFACE ...............12
3.1 DDR2 Channel
............................................................................................................................12
.................................................................................................................12
3.3 FBD Channel Latency
..................................................................................................................13
3.4 Peak Theoretical Throughput
........................................................................................................13
3.2 SMBus Slave Interface
......................................................................................................................................13
3.6 Hot remove
................................................................................................................................. 13
3.7 Hot replace
.................................................................................................................................13
4. PIN CONFIGUREATION ................................................................................................................14
5.0 FBDIMM FUNCTIONAL BLOCK DIAGRAM ...............................................................................16
5.1 512MB, 64Mx72 Module - M395T6553CZ4
.......................................................................................16
5.2 1GB, 128Mx72 Module - M395T2953CZ4
.........................................................................................17
5.3 2GB, 256Mx72 Module - M395T5750CZ4
.........................................................................................18
6.0 ELECTRICAL CHARACTERISTICS ............................................................................................19
7.0 CHANNEL INITIALIZATION ........................................................................................................25
3.5 Hot-add
2 of 31
Rev. 1.4 April 2007
FBDIMM
Revision History
Revision
1.0
1.1
1.2
1.3
1.4
Month
May
June
June
September
April
Year
2006
2006
2006
2006
2007
- First Released.
- The typo in Features was corrected.
- Updated Reference Clock Frequency in Table12
- Changed Part Number
- Changed AMB device operation temperature symbol(Tj to Tcase)
History
DDR2 SDRAM
3 of 31
Rev. 1.4 April 2007
FBDIMM
1.0 FEATURES
- 240pin fully buffered dual in-line memory module (FB-
DIMM)
- 3.2Gb/s, 4.0Gb/s link transfer rate
- 1.8V +/- 0.1V Power Supply for DRAM VDD/VDDQ
- 1.5V +0.075/-0.045V Power Supply for AMB VCC
- 3.3V +/- 0.3V Power Supply for VDDSPD
- Buffer Interface with high-speed differential point-to-
point Link at 1.5 volt
- Channel error detection & reporting
-
-
-
-
-
-
-
-
-
DDR2 SDRAM
Channel fail over mode support
Serial presence detect with EEPROM
4 Banks
Posted CAS
Programmable CAS Latency: 3, 4, 5
Automatic DDR2 DRAM bus and channel calibration
MBIST and IBIST Test functions
Hot add-on and Hot Remove Capability
Transparent mode for DRAM test support
Table 1 : Ordering Information
Part Number
M395T6553CZ4-CD50/E60
M395T6553CZ4-CD51/E61
M395T2953CZ4-CD50/E60
M395T2953CZ4-CD51/E61
M395T5750CZ4-CD50/E60
M395T5750CZ4-CD51/E61
Density
512MB
1GB
2GB
Organization
64M x 72
128M x 72
256M x 72
Component Composition
64Mx8(K4T51083QC)
* 9EA
64Mx8(K4T51083QC)
* 18EA
128Mx4(K4T51043QC)
* 36EA
Number of AMB Ven- Type of Heat
Rank
dor
Spreader
1
2
2
Intel
IDT
Intel
IDT
Intel
IDT
Full Module
30.35mm
Height
Note :
1. “Z” of Part number(11th digit) stands for Lead-free products.
2. The last digit stands for AMB vendor.
Table 2
:
Performance range
E6(DDR2-667)
DDR2 DRAM Speed
CL-tRCD-tRP
667
5-5-5
D5(DDR2-533)
533
4-4-4
Unit
Mbps
CK
Table 3 : Address Configuration
Organization
64Mx8(512Mb) based Module
128Mx4(512Mb) based Module
Row Address
A0-A13
A0-A13
Column Address
A0-A9
A0-A9, A11
Bank Address
BA0-BA1
BA0-BA1
Auto Precharge
A10
A10
4 of 31
Rev. 1.4 April 2007
FBDIMM
2.0 FBDIMM GENERALS
2.1 FB-DIMM Operation Overview
DDR2 SDRAM
FB-DIMM (Fully Buffered Dual in Line Memory Module) is designed for the applications which require higher data transfer bandwidth and
scalable memory capacity. The memory slot access rate per channel decreases as the memory bus speed increases, resulting in limited
density build-up as channel speeds increase with memory system having the stub-bus architecture. FB-DIMM solution is intended to
eliminate this stub-bus channel bottleneck by using point-to-point links that enable multiple memory modules to be connected serially to
a given channel.
Memory system architecture perspective, FB-DIMM is fully differentiated from Registered DIMM and Unbuffered DIMM. A lot of new
technologies are integrated into this solution in order to achieve this scalable higher speed memory solution. Serial link interface with
packet data format and dedicated read/write paths are key attribute in FB-DIMM protocol. Point to Point interconnect with fully differential
signaling and de-emphasis scheme are key attribute in FBD channel link. Clock recovery by using data stream is key attribute in FBD
clocking. FB-DIMM supports both clock resync and resampling mode options. CRC (Cyclic Redundancy Check) bits are transferred with
data stream for reliability at high speed data transaction. Failover mechanism supports system running with dynamic IO failure. Finally all
FB-DIMM is connected in daisy chain manner. Thus, every interconnection between AMB (advanced memory buffer) to AMB, AMB to
Host and AMB to DRAM, is point to point interconnection which allows higher data transfer bandwidth.
Figure 1 shows a lot of new technologies integrated with FBD solution
Figure 1 : FB-DIMM Memory System Overview
DRAM
Two unidirectional links
- Northbound
- Southbound
Protocol Packet
ADDR.CMD, DATA
DRAM
SB (ADDR, CMD, Wdata)
Host
NB(Rdata)
DQs ADDR CLK
CMD
Rx
Tx
Tx
AMB
Rx
Tx
Rx
AMB
Tx
Rx
CLK
Daisy Chain
Connection
Upto 8 AMB
Clk_Ref
ADDR
DQs CMD
P2P Interconnect
- LVDS
- De-Emphasis
DRAM
Reliability
Clock Recovery
- CRC fail-over
DRAM
DIMM Topology
Fly-by CLK, CMD
FIFO
Buffer
Clock
5 of 31
Rev. 1.4 April 2007
京公网安备 11010802033920号
EEWORLD
