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IMP5241CDB

Description
Interface Circuit
CategoryAnalog mixed-signal IC    Drivers and interfaces   
File Size295KB,10 Pages
ManufacturerA1 PROS
Websitehttp://www.a1pros.co.kr/new/
Download Datasheet Parametric Compare View All

IMP5241CDB Overview

Interface Circuit

IMP5241CDB Parametric

Parameter NameAttribute value
package instruction,
Reach Compliance Codeunknown
Base Number Matches1
1
IMP52 4 1/42/43
D
ATA
C
OMMUNICATIONS
9-Line Multimode LVD/SE
SCSI Terminator
The IMP5241/42/43 is a multimode SCSI terminator that conforms to the
SCSI Parallel Interconnect-2 (SPI-2) specification developed by the T10
standards committee for low voltage differential (LVD) termination,
while providing backwards compatibility to the SCSI, SCSI-2, and SPI
single-ended specifications. Multimode compatibility permits the use of
legacy devices on the bus without hardware alterations. Automatic mode
selection is achieved through voltage detection on the diffsense line.
The IMP5241/42/43 delivers the ultimate in SCSI bus performance while
saving component cost and board area. Elimination of the external capac-
itors also mitigates the need for a lengthy capacitor selection process. The
individual high bandwidth drivers also maximize channel separation
and reduce channel to channel noise and cross talk. The high bandwidth
architecture insures ULTRA2 performance while providing a clear migra-
tion path to ULTRA3 and beyond.
When the IMP5241/42/43 is enabled, the differential sense (DIFFSENSE)
pin supplies a voltage between 1.2V and 1.4V. In application, this pin is
tied to the DIFFSENSE input of the corresponding LVD transceivers. This
action enables the LVD transceiver function. DIFFSENSE is capable of
supplying a maximum of 15mA. Tying the DIFFSENSE pin HIGH places
the IMP5241/42/43 in a high impedance state indicating the presence of
an HVD device. Tying the pin LOW places the part in a single-ended
mode while also signaling the multimode transceiver to operate in a sin-
gle-ended mode.
Recognizing the needs of portable and configurable peripherals, the
IMP5241/42/43 have a TTL compatible sleep/disable mode. During this
Key Features
N
N
N
N
N
N
N
N
N
N
N
N
Auto-selectable LVD or single-ended termination
3.0pF maximum disabled output capacitance
Fast response, no external capacitors required
Compatible with active negation drivers
15µA supply current in disconnect mode
Logic command disconnects all termination lines
DIFFSENSE line driver
Ground driver integrated for single-ended
operation
Current limit and thermal protection
Hot-swap compatible (single-ended)
Compatible with SCSI 1, 2, 3, FAST-20, and the
pending SPI-2 LVD
Pin compatible with DS2118, UCC5630 and
LX5241/42/43
sleep/disable mode, power dissipation is reduced to a
meager 15µA while also placing all outputs in a high
impedance state. Also during sleep/disable mode, the
DIFFSENSE function is disabled and is placed in a high
impedance state.
Another key feature of the IMP5241/42/43 is the mas-
ter/slave function. Driving this pin HIGH or floating the
pin enables the 1.3V DIFFSENSE reference. Driving the pin
LOW disables the on board DIFFSENSE reference and
enables use of an external master reference device.
Block Diagram
V
TERM
DISCONNECT
(IMP5241)
DISCONNECT
(IMP5242)
LVD
1.25V
M/S
10mA
1.07mA
MODE Control & Delay
Window SE
Comp.
HVD
20kΩ
DIFF B
Power ON
LVD
Power ON & MODE Delay
5241/42_01.eps
SE 2.85V, 22.5mA
Internal V
REF
1.30V
Power ON
SE
2.2V
1.07mA
200
52.5
52.5
20
SE
DISC/HVD
LVD
1 of 9
LVD(-) / SE
SE
HVD
LVD
LVD(+) / SE
(Pseudo-GND)
Latch
SE
HVD
LVD
DIFFSENSE
© 2001 IMP, Inc.
Data Communications
1

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Reach Compliance Code unknown unknown unknown unknown unknown unknown
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