KM6161000B Family
Document Title
64K x16 bit Low Power CMOS Static RAM
CMOS SRAM
Revision History
Revision No. History
0.0
1.0
Initial draft
Finalize
- One datasheet for commercial and industrial part.
Revised
- Change datasheet format.
- Remove Icc write current value.
- Remove low power product from product
Draft Data
August 12, 1995
April 15, 1996
Remark
Preliminary
Final
2.0
February 12, 1998
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 2.0
February 1998
KM6161000B Family
64K x16 bit Low Power CMOS Static RAM
FEATURES SUMMARY
• Process Technology: Poly Load
• Organization: 64K x16
• Data Byte Control: LB=I/O
1
~
8
, UB=I/O
9
~
16
• Power Supply Voltage: 4.5~5.5V
• Low Data Retention Voltage: 2V(Min)
• Three state output and TTL Compatible
• Package Type: 44-TSOP2-400F/R
CMOS SRAM
GENERAL DESCRIPTION
The KM6161000B families are fabricated by SAMSUNG′s
advanced CMOS process technology. The families support
various operating temperature ranges and have various pack-
age types for user flexibility of system design. The families
also support low data retention voltage for battery back-up
operation with low data retention current.
PRODUCT FAMILY
Power Dissipation
Product Family
KM6161000BL-L
KM6161000BLI-L
Operating Temperature
Commercial(0~70°C)
4.5 to 5.5V
Industrial(-40~85°C)
70/100ns
50µA
1. The parameter is measured with 30pF test load.
Vcc Range
Speed
55*/70ns
Standby
(I
SB1
, Max)
20µA
Operating
(I
CC2
, Max)
120mA
PKG Type
44-TSOP2-F/R
PIN DESCRIPTION
A4
A3
A2
A1
A0
CS
I/OI
I/O2
I/O3
I/O4
Vcc
Vss
I/O5
I/O6
I/O7
I/O8
WE
A15
A14
A13
A12
N.C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
Vss
Vcc
I/O12
I/O11
I/O10
I/O9
N.C
A8
A9
A10
A11
N.C
A5
A6
A7
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
Vss
Vcc
I/O12
I/O11
I/O10
I/O9
N.C
A8
A9
A10
A11
N.C
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A4
A3
A2
A1
A0
CS
I/OI
I/O2
I/O3
I/O4
Vcc
Vss
I/O5
I/O6
I/O7
I/O8
WE
A15
A14
A13
A12
N.C
FUNCTIONAL BLOCK DIAGRAM
Clk gen.
A0
A1
A2
A3
A4
A5
A6
A7
A8
A15
Precharge circuit.
Vcc
Vss
Row
select
Memory array
1024 rows
64×16 columns
44-TSOP2
Forward
44-TSOP2
Reverse
I/O
1
~I/O
8
Data
cont
Data
cont
Data
cont
A9
I/O Circuit
Column select
I/O
9
~I/O
16
Name
CS
OE
WE
Function
Chip Select Input
Output Enable Input
Write Enable Input
Name
Vcc
Vss
LB
UB
N.C
Power
Function
A10 A11 A12 A13 A14
Ground
Lower Byte (I/O
1~8
)
Upper Byte(I/O
9~16
)
No Connection
WE
OE
UB
LB
CS
A
0
~A
15
Address Inputs
I/O
1
~
16
Data Inputs/Outputs
Control
logic
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to change products and specifications without notice.
2
Revision 2.0
February 1998
KM6161000B Family
PRODUCT LIST
Commercial Temperature Product(0~70°C)
Part Name
KM6161000BLT-5L
KM6161000BLT-7L
KM6161000BLR-5L
KM6161000BLR-7L
Function
44-TSOP2-F, 5V, 55ns, LL-pwr
44-TSOP2-F, 5V, 70ns, LL-pwr
44-TSOP2-R, 5V, 55ns, LL-pwr
44-TSOP2-R, 5V, 70ns, LL-pwr
CMOS SRAM
Industrial Temperature Products(-40~85°C)
Part Name
KM6161000BLTI-7L
KM6161000BLTI-10L
KM6161000BLRI-7L
KM6161000BLRI-10L
Function
44-TSOP2-F, 5V, 70ns, LL-pwr
44-TSOP2-F, 5V, 100ns, LL-pwr
44-TSOP2-R, 5V, 70ns, LL-pwr
44-TSOP2-R, 5V, 100ns, LL-pwr
FUNCTIONAL DESCRIPTION
CS
H
L
L
L
L
L
L
L
L
OE
X
1)
H
X
1)
L
L
L
X
1)
X
1)
X
1)
WE
X
1)
H
X
1)
H
H
H
L
L
L
LB
X
1)
X
1)
H
L
H
L
L
H
L
UB
X
1)
X
1)
H
H
L
L
H
L
L
I/O
1~8
High-Z
High-Z
High-Z
Dout
High-Z
Dout
Din
High-Z
Din
I/O
9~16
High-Z
High-Z
High-Z
High-Z
Dout
Dout
High-Z
Din
Din
Mode
Deselected
Output Disabled
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
Lower Byte Write
Upper Byte Write
Word Write
Power
Standby
Active
Active
Active
Active
Active
Active
Active
Active
1. X means don′t care. (Must be in low or high state)
ABSOLUTE MAXIMUM RATINGS
1)
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Storage temperature
Operating Temperature
Soldering temperature and time
Symbol
V
IN
,V
OUT
V
CC
P
D
T
STG
T
A
T
SOLDER
Ratings
-0.5 to Vcc+0.5
-0.5 to 7.0
1.0
-65 to 150
0 to 70
-40 to 85
260°C, 10sec(Lead Only)
Unit
V
V
W
°C
°C
°C
-
Remark
-
-
-
-
KM6161000BL-L
KM6161000BLI-L
-
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3
Revision 2.0
February 1998
KM6161000B Family
RECOMMENDED DC OPERATING CONDITIONS
1)
Item
Supply voltage
Ground
Input high voltage
Input low voltage
Symbol
Vcc
Vss
V
IH
V
IL
Min
4.5
0
2.2
-0.5
3)
Typ
5
0
-
-
CMOS SRAM
Max
5.5
0
V
CC
+0.5
2)
0.8
Unit
V
V
V
V
Note:
1. Commercial Product : T
A
=0 to 70°C, otherwise specified
Industrial Product : T
A
=-40 to 85°C, otherwise specified
2. Overshoot : V
CC
+3.0V in case of pulse width
≤
30ns
3. Undershoot : -3.0V in case of pulse width
≤
30ns
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE
1)
(f=1MHz, T
A
=25°C)
Item
Input capacitance
Input/Output capacitance
1. Capacitance is sampled, not 100% tested
Symbol
C
IN
C
IO
Test Condition
V
IN
=0V
V
IO
=0V
Min
-
-
Max
6
8
Unit
pF
pF
DC AND OPERATING CHARACTERISTICS
Item
Input leakage current
Output leakage current
Operating power supply
Symbol
I
LI
I
LO
I
CC
I
CC1
I
CC2
Output low voltage
Output high voltage
Standby Current(TTL)
Standby Current(CMOS)
1. Industrial Product = 50µA
Test Conditions
V
IN
=V
SS
to V
CC
CS=V
IH
or OE=V
IH
or WE=V
IL,
V
IO
=V
SS
to V
CC
Min
-1
-1
-
Read
Write
-
-
-
-
2.4
-
-
Typ
-
-
-
-
-
-
-
-
-
-
Max
1
1
10
15
40
120
0.4
-
3
20
1)
Unit
µA
µA
mA
mA
mA
V
V
mA
µA
I
IO
=0mA, CS=V
IL
, V
IN
=V
IL
or V
IH,
Read
Cycle time=1µs, 100% duty, I
IO
=0mA
CS≤0.2V, V
IN
≤0.2V
or V
IN
≥Vcc-0.2V
Average operating current
Cycle time=Min, 100% duty, I
IO
=0mA, CS=V
IL
, V
IN
=V
IL
or V
IH
I
OL
=2.1mA
I
OH
=-1.0mA
CS=V
IH
, Other inputs=V
IL
or V
IH
CS≥V
CC
-0.2V, Other inputs=0∼V
CC
V
OL
V
OH
I
SB
I
SB1
4
Revision 2.0
February 1998
KM6161000B Family
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Test Input/Output Reference)
CMOS SRAM
Input pulse level : 0.8 to 2.4V
Input rising and falling time : 5ns
Input and output reference voltage : 1.5V
Output load (See right) :C
L
=100pF+1TTL
C
L
=30pF+1TTL
C
L
1)
1. Including scope and jig capacitance
AC CHARACTERISTICS
Speed Bins
Parameter List
Read cycle time
Address access time
Chip select to output
Output enable to valid output
UB,LB Access Time
Read
Chip select to low-Z output
UB,LB enable to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
UB,LB disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write cycle time
Chip select to end of write
Address set-up time
Address valid to end of write
Write pulse width
Write
UB, LB valid to end of write
Write recovery time
Write to output high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
Symbol
t
RC
t
AA
t
CO
t
OE
t
BA
t
LZ
t
BLZ
t
OLZ
t
HZ
t
BHZ
t
OHZ
t
OH
t
WC
t
CW
t
AS
t
AW
t
WP
t
BW
t
WR
t
WHZ
t
DW
t
DH
t
OW
55
-
-
-
-
10
5
5
0
0
0
10
55
45
0
45
40
45
0
0
25
0
5
55ns
Min
Max
-
55
55
25
25
-
-
-
20
20
20
-
-
-
-
-
-
-
-
25
-
-
-
70
-
-
-
-
10
5
5
0
0
0
15
70
60
0
60
50
60
0
0
30
0
5
70ns
Min
Max
-
70
70
35
35
-
-
-
25
25
25
-
-
-
-
-
-
-
-
30
-
-
-
100ns
Min
100
-
-
-
-
10
5
5
0
0
0
15
100
80
0
80
70
80
0
0
40
0
5
Max
-
100
100
50
50
-
-
-
30
30
30
-
-
-
-
-
-
-
-
35
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
DATA RETENTION CHARACTERISTICS
Item
V
CC
for data retention
Data retention current
Data retention set-up time
Recovery time
Symbol
V
DR
I
DR
t
SDR
t
RDR
Test Condition
CS≥Vcc-0.2V
V
CC
=3.0V, CS≥Vcc-0.2V
See data retention waveform
Min
2.0
-
0
5
Typ
-
-
-
-
Max
5.5
15
-
-
Unit
V
µA
ms
5
Revision 2.0
February 1998
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