PO100HSTL11A
1 to 2 Differential Clock/Data Fanout Buffer
2.4V -3.6V Differential inputs to HSTL outputs Clock Buffer
02/11/07
FEATURES:
• Patented Technology
• Two HSTL differential outputs
• One pair of LVDS/LVPECL/HSTL/ differential
or single-ended inputs
• Operating frequency up to 1.24GHz with 2pf load
• Operating frequency up to 900MHz with 5pf load
• Operating frequency up to 400MHz with 15pf load
• Very low output pin to pin skew < 40ps
• Propagation delay < 2.0ns max with 15pf load
• 2.4V to 3.6V power supply
• Industrial temperature range: –40°C to 85°C
• Available in 8-pin SOIC package
• Available in 8-pin TSSOP package
DESCRIPTION:
Potato Semiconductor’s PO100HSTL11A is
designed for world top performance using
submicron CMOS technology to achieve 1.24GHz
HSTL output frequency with less than 2.0ns
propagation delay.
The
PO100HSTL11A
is a low-skew, 1-to-2
differential fanout buffer targeted to meet the
requirements of high-performance clock and data
distribution applications. The device has a fully
differential internal architecture that is optimized
to achieve low signal skews at operating frequen-
cies of up to 1.24GHz .
Pin Configuration
Logic Block Diagram
Q0
Q0
Q0
Q1
Q1
1
2
3
4
8
7
6
5
Vcc
D
Q0
D
D
GND
D
Q1
Q1
Pin Description
PIN
D, D
Q0, Q0, Q1, Q1
V
CC
GND
FUNCTION
LVDS LVPECL HSTL Inputs
HSTL Outputs
Positive Supply
Ground Supply
1
Copyright
© Potato Semiconductor Corporation
PO100HSTL11A
1 to 2 Differential Clock/Data Fanout Buffer
2.4V -3.6V Differential inputs to HSTL outputs Clock Buffer
02/11/07
Maximum Ratings
Description
Storage Temperature
Operation Temperature
Operation Voltage
Input Voltage
Output Voltage
Max
-65 to 150
-40 to 85
-0.5 to +4.6
-0.5 to Vcc
-0.5 to Vcc+0.5
Unit
°C
°C
V
V
V
Note:
stresses greater than listed under
Maximum
Ratings
may
cause
permanent damage to the device. This
is a stress rating only and functional
operation of the device at these or any
other conditions above those indicated
in the operational sections of this
specification is not implied. Exposure
to absolute maximum rating conditions
for extended periods may affect
reliability specification is not implied.
Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
88
88
Maximum
Units
pF
K
Ω
K
Ω
DC Electrical Characteristics
Symbol
Description
Output High voltage
Output Low voltage
Input High voltage
Input Low voltage
Input High current
Input Low current
Clamp diode voltage
Test Conditions
Vcc=3V Vin=V
IH
or V
IL
, I
OH
= -12mA
Vcc=3V Vin=V
IH
or V
IL
, I
OH
=12mA
Guaranteed Logic HIGH Level (Input Pin)
Guaranteed Logic LOW Level (Input Pin)
Vcc = 3.6V and Vin = Vcc
Vcc = 3.6V and Vin = 0V
Vcc = Min. And
I
IN
= -18mA
Min
Typ
Max
Unit
V
OH
V
OL
V
IH
V
IL
I
IH
I
IL
V
IK
Notes:
1.
2.
3.
4.
5.
2.4
-
2
-0.5
-
-
-
3
0.3
-
-
-
-
-0.7
-
0.5
Vcc
0.8
1
-1
-1.2
V
V
V
V
uA
uA
V
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, 25
°C
ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
VoH = Vcc – 0.6V at rated current
2
Copyright
© Potato Semiconductor Corporation
PO100HSTL11A
1 to 2 Differential Clock/Data Fanout Buffer
2.4V -3.6V Differential inputs to HSTL outputs Clock Buffer
02/08/07
Power Supply Characteristics
Symbol
Description
Quiescent Power Supply Current
Test Conditions (1)
Vcc=Max, Vin=Vcc or GND
Min
Typ
Max
Unit
Icc
Q
Notes:
1.
2.
3.
4.
-
0.1
30
uA
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, 25°C ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
Switching Characteristics
Symbol
Description
Propagation Delay D to Output pair
Test Conditions (1)
CL = 15pF
0.8V – 2.0V
CL = 15pF, 125MHz
CL = 15pF, 125MHz
CL =15pF
CL = 5pF
CL = 2pF
M ax
Unit
t
PD
tr/tf
tsk(o)
tsk(pp)
fmax
fmax
fmax
Notes:
2.0
0.8
40
250
400
250
900
300
1240
400
ns
ns
ps
ps
MHz
MHz
MHz
Rise/Fall Time
Output Pin to Pin Skew (Same Package)
Output Skew (Different Package)
Input Frequency
Input Frequency
Input Frequency
1. See test circuits and waveforms.
2. tpLH, tpHL, tsk(p), and tsk(o) are production tested. All other parameters guaranteed but not production tested.
3. Airflow of 1m/s is recommended for frequencies above 133MHz
Test Circuit
50
Ω
15pF
to
2pF
50
Ω
15pF
to
2pF
3
Copyright
© Potato Semiconductor Corporation
PO100HSTL11A
1 to 2 Differential Clock/Data Fanout Buffer
2.4V -3.6V Differential inputs to HSTL outputs Clock Buffer
02/08/07
Test Waveforms
FIGURE 1. LVDS/ PECL/ ECL/ HSTL /DIFFERENTIAL INPUT WAVEFORM DEFINITIONS
VCC
VCC= 3.3V
VIH
VPP
VIL
VEE=0.0V
VEE
VPP RANGE
0V-VCC
FIGURE 2. HSTL/HSTL OUTPUT
tr,tf,
20-80%
VO
FIGURE 3. Propogation Delay, Output pulse skew, and output-to-output skew
for D to output pair
INPUT
CLOCK
VPP
TPLH
TPD
OUTPUT
CLOCK
TPHL
VO
tSK(O)
ANOTHER
OUTPUT
CLOCK
4
Copyright
© Potato Semiconductor Corporation
PO100HSTL11A
1 to 2 Differential Clock/Data Fanout Buffer
2.4V -3.6V Differential inputs to HSTL outputs Clock Buffer
02/11/07
Packaging Mechanical Drawing: 8 pin SOIC
8
.0099
.0196
0.25
x 45˚
0.50
0-8˚
.149
.157
3.78
3.99
.016
.050
0.40
1.27
.2284
.2440
5.80
6.20
1
.189
.196
.016
.026
0.406
0.660
REF
.050
BSC
1.27
.013 0.330
.020 0.508
.0040 0.10
.0098 0.25
X.XX DENOTES DIMENSIONS
X.XX IN MILLIMETERS
4.80
5.00
.053
.068
1.35
1.75
SEATING PLANE
.0075
.0098
0.19
0.25
Packaging Mechanical Drawing: 8 pin TSSOP
8
SEATING PLANE
X.XX DENOTES DIMENSIONS
X.XX IN MILLIMETERS
5
Copyright
© 2006, Potato Semiconductor Corporation
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