Z8018010PSG datasheet, PDF - EEWORLD Datasheet

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Z8018010PSG: DescriptionMicroprocessor, CMOS, PDIP64, DIP-64; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，124 Pages; ManufacturerIXYS; Environmental Compliance

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Z8018010PSG Overview

Microprocessor, CMOS, PDIP64, DIP-64

Z8018010PSG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IXYS
Parts packaging code	DIP
package instruction	SDIP,
Contacts	64
Reach Compliance Code	compliant
Other features	DYNAMIC REFRESH CONTROL; 1M BYTE PHYSICAL MEMORY
JESD-30 code	R-PDIP-T64
JESD-609 code	e3
length	57.785 mm
Number of terminals	64
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	SDIP
Package shape	RECTANGULAR
Package form	IN-LINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	5.01 mm
Maximum slew rate	60 mA
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	MATTE TIN
Terminal form	THROUGH-HOLE
Terminal pitch	1.78 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	19.05 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR
Base Number Matches	1

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Z80180

Microprocessor Unit

Product Specification

PS014003-0603

Z80180

Microprocessor Unit

iii

Table of Contents

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Multiplexed Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . 15

Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . .

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ASCI Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ASCI Transmit Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . .

Channel 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ASCI Receive Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Channel 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PS014003-0603

Table of Contents

Z80180

Microprocessor Unit

DMA Memory Address Register Channel 1 . . . . . . . . . . . . . . . . 83

DMA Memory Address Register, Channel 1L . . . . . . . . . . . 84

DMA Memory Address Register, Channel 1H . . . . . . . . . . . 84

DMA I/O Address Register Channel 1 . . . . . . . . . . . . . . . . . . . . 85

DMA I/O Address Register Channel 1L . . . . . . . . . . . . . . . . 86

DMA I/O Address Register Channel 1H . . . . . . . . . . . . . . . . 86

DMA I/O Address Register Channel 1B . . . . . . . . . . . . . . . . 87

DMA Status Register (DSTAT) . . . . . . . . . . . . . . . . . . . . . . 87

Mnemonic DSTAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

DMA Mode Register (DMODE) . . . . . . . . . . . . . . . . . . . . . . 89

Mnemonic DMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

DMA/WAIT Control Register (DCNTL) . . . . . . . . . . . . . . . . . . . . 92

Interrupt Vector Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Mnemonic: IL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Int/TRAP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Mnemonics ITC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Refresh Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Mnemonic RCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

MMU Common Base Register . . . . . . . . . . . . . . . . . . . . . . . . . 101

Mnemonic CBR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

MMU Bank Base Register (BBR) . . . . . . . . . . . . . . . . . . . . . . . 102

Mnemonic BBR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

MMU Common/Bank Area Register (CBAR) . . . . . . . . . . . . . . 103

Mnemonic CBAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Operation Mode Control Register . . . . . . . . . . . . . . . . . . . . . . 104

Mnemonic OMCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

I/O Control Register (ICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Table of Contents

PS014002-0403

Z8018010PSG Related Products

	Z8018010PSG	Z8018010FSG	Z8018010PSC	Z8018010FSC	Z8018010VSG
Description	Microprocessor, CMOS, PDIP64, DIP-64	Microprocessor, CMOS, PQFP80, QFP-80	Microprocessor, 8-Bit, 10MHz, CMOS, PDIP64, DIP-64	Microprocessor, 8-Bit, 10MHz, CMOS, PQFP80, QFP-80	Microcontroller, 8-Bit, 10MHz, CMOS, PQCC68, LCC-68
Is it lead-free?	Lead free	Lead free	Contains lead	Contains lead	Lead free
Is it Rohs certified?	conform to	conform to	incompatible	incompatible	conform to
Maker	IXYS	IXYS	IXYS	IXYS	IXYS
Parts packaging code	DIP	QFP	DIP	QFP	LCC
package instruction	SDIP,	QFP,	DIP-64	QFP-80	LCC-68
Contacts	64	80	64	80	68
Reach Compliance Code	compliant	compliant	unknown	unknown	compliant
Other features	DYNAMIC REFRESH CONTROL; 1M BYTE PHYSICAL MEMORY	DYNAMIC REFRESH CONTROL; 1M BYTE PHYSICAL MEMORY	DYNAMIC REFRESH CONTROL; 1M BYTE PHYSICAL MEMORY	DYNAMIC REFRESH CONTROL; 1M BYTE PHYSICAL MEMORY	DYNAMIC REFRESH CONTROL; 1M BYTE PHYSICAL MEMORY
JESD-30 code	R-PDIP-T64	R-PQFP-G80	R-PDIP-T64	R-PQFP-G80	S-PQCC-J68
JESD-609 code	e3	e3	e0	e0	e3
length	57.785 mm	20 mm	57.785 mm	20 mm	24.23 mm
Number of terminals	64	80	64	80	68
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SDIP	QFP	SDIP	QFP	QCCJ
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	SQUARE
Package form	IN-LINE, SHRINK PITCH	FLATPACK	IN-LINE, SHRINK PITCH	FLATPACK	CHIP CARRIER
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	260	225	225	260
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	5.01 mm	3.1 mm	5.01 mm	3.1 mm	4.57 mm
Maximum slew rate	60 mA	60 mA	60 mA	60 mA	60 mA
Nominal supply voltage	5 V	5 V	5 V	5 V	5 V
surface mount	NO	YES	NO	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	MATTE TIN	Matte Tin (Sn)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	MATTE TIN
Terminal form	THROUGH-HOLE	GULL WING	THROUGH-HOLE	GULL WING	J BEND
Terminal pitch	1.78 mm	0.8 mm	1.78 mm	0.8 mm	1.27 mm
Terminal location	DUAL	QUAD	DUAL	QUAD	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED	40	30	30	40
width	19.05 mm	14 mm	19.05 mm	14 mm	24.23 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROCONTROLLER
Maximum supply voltage	5.5 V	-	5.5 V	5.5 V	5.5 V
Minimum supply voltage	4.5 V	-	4.5 V	4.5 V	4.5 V
bit size	-	8	8	8	8
speed	-	10 MHz	10 MHz	10 MHz	10 MHz

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Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

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