DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD16640B
300/309-OUTPUT TFT-LCD SOURCE DRIVER (64-GRAY SCALE)
The
µ
PD16640B is a source driver for TFT-LCD 64 gray scale displays. Its logic circuit operates at 3.3 V and the
driver circuit operates at 3.3 or 5.0 V (selectable). The input data is digital data at 6 bits
×
3 dots, and 260,000 colors
can be displayed in 64-value outputs
γ-corrected
by the internal D/A converter and 11 external power supplies.
The clock frequency is 55 MHz MIN.
By switching over the number of outputs between 300 and 309, the
µ
PD16640B can be used in TFT-LCD panels conforming to the SVGA/XGA standards.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
CMOS level input
6 bits (gray scale data)
×
3 dots input
64-value output by 11 external power supplies and internal D/A converter
Output voltage range: V
SS2
+ 0.1 V to V
DD2
– 0.1 V
High-speed data transfer: f
MAX
. = 55 MHz MIN. (internal data transfer speed when operating at 3.0 V)
Precharge-less output buffer
Level of
γ-corrected
power supply can be inverted
Number of outputs selectable (O
sel
= H: 300 outputs, O
sel
= L: 309 outputs)
Supply voltage of driver circuit selectable (V
sel
= H: 3.3 V, V
sel
= L: 5.0 V)
Slim TCP
Input data inversion function (INV)
Logic power supply (V
DD1
): 3.3 V
±
0.3 V
Driver power supply (V
DD2
): 3.3 V
±
0.3 V (V
sel
= H)
5.0 V
±
0.5 V (V
sel
= L)
ORDERING INFORMATION
Part Number
Package
TCP (TAB package)
µ
PD16640BN- xxx
Remark
The TCP’s external shape is custom-order item. Users are requested to consult with a NEC sales
representative.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S12581EJ1V0DS00 (1st edition)
Date Published March 1999 NS CP(K)
Printed in Japan
The mark
5
shows major revised points.
©
1998
µ
PD16640B
1. BLOCK DIAGRAM
STHR
R,/L
CLK
O
sel
103-bit bidirectional shift register
C
1
C
2
C
102
C
103
STHL
V
DD1
V
SS1
D
00
to
D
05
D
10
to D
15
D
20
to D
25
INV
Data register
STB
Latch
V
sel
D/A converter
V
0
to
V
10
V
DD2
V
SS2
Voltage follower output
S
1
S
2
S
3
S
309
Remark
/xxx indicates active low signal.
2
Data Sheet S12581EJ1V0DS00
µ
PD16640B
2. PIN CONFIGURATION (
µ
PD16640BN-xxx)
S
309
S
308
S
307
V
sel
V
SS2
V
DD2
V
10
V
8
V
6
V
4
V
2
V
0
R,/L
D
20
D
21
D
22
D
23
D
24
D
25
STB
STHL
V
DD1
CLK
V
SS1
STHR
INV
D
10
D
11
D
12
D
13
D
14
D
15
D
00
D
01
D
02
D
03
D
04
D
05
V
1
V
3
V
5
V
7
V
9
V
DD2
V
SS2
O
sel
Copper Foil
Surface
S
3
S
2
S
1
Remark
O
sel
and V
sel
pins are internally pulled up.
Therefore, the number of input pins can be reduced by opening or short-circuiting these
pins to V
SS2
by means of TCP wiring.
Data Sheet S12581EJ1V0DS00
3
µ
PD16640B
3. PIN DESCRIPTION
Pin Symbol
S
1
to S
309
Pin Name
Driver output
Description
Output 64 gray scale analog voltages converted from digital signals.
O
sel
= H: 300 outputs (S
1
→
S
150
, S
160
→
S
309
)
O
sel
= L: 309 outputs (S
1
→
S
309
)
Output pins S
151
to S
159
are invalid in 300-output mode.
Inputs 18-bit-wide display gray scale data (6 bits)
×
3 dots (RGB).
D
X0
: LSB, D
X5
: MSB
D
00
to D
05
D
10
to D
15
D
20
to D
25
R,/L
Display data input
Shift direction select input
This pin inputs/outputs start pulses in cascade mode.
Shift direction of shift register is as follows:
R/L = H: STHR input, S
1
→
S
309
, STHL output
R/L = L : STHL input, S
309
→
S
1
, STHR output
R/L = H: Inputs start pulse.
R/L = L : Outputs start pulse.
R/L = H: Outputs start pulse.
R/L = L : Inputs start pulse.
Selects number of outputs. This pin is internally pulled up by V
DD1
power supply.
O
sel
= H: 300 outputs
O
sel
= L: 309 outputs
Selects driver voltage. This pin is internally pulled up by V
DD2
power supply.
V
sel
= H: V
DD2
= 3.3 V
V
sel
= L: V
DD2
= 5.0 V
Inputs shift clock to shift register. Display data is loaded to data register at rising
edge of this pin.
When O
sel
= H, start pulse output goes high at rising edge of 100th clock after start
pulse has been input, and serves as start pulse to driver in next stage. 100th clock
of driver in first stage serves as start pulse of driver in next stage.
When O
sel
= L, start pulse output goes high at rising edge of 103rd clock after start
pulse has been input, and serves as start pulse to driver in next stage. 103rd clock
of driver in first stage serves as start pulse of driver in next stage.
Contents of data register are latched at rising edge, transferred to D/A converter,
and output as analog voltage corresponding to display data. Contents of internal
shift register are cleared after STB has been input. One pulse of this signal is input
when
µ
PD16640B is started, and then device operates normally. For STB input
timing, refer to
8. Switching Characteristic Waveform.
Inputs
γ-corrected
power from external source.
V
SS2
+ 0.1 V≤ V
10
≤
V
9
≤
V
8
≤
V
7
≤
V
6
≤
V
5
≤
V
4
≤
V
3
≤
V
2
≤
V
1
≤
V
0
≤
V
DD2
– 0.1 V or
V
SS2
+ 0.1 V
≤
V
0
≤
V
1
≤
V
2
≤
V
3
≤
V
4
≤
V
5
≤
V
6
≤
V
7
≤
V
8
≤
V
9
≤
V
10
≤
V
DD2
– 0.1 V
Maintain gray scale power supply during gray scale voltage output.
Input data can be inverted when display data is loaded.
INV = H: Inverts and loads input data.
INV = L: Does not invert input data.
3.3 V ± 0.3 V
V
sel
= H : V
DD2
= 3.3 V ± 0.3 V
V
sel
= L : V
DD2
= 5.0 V ± 0.5 V
Ground
Ground
STHR
STHL
O
sel
Right shift start pulse I/O
Left shift start pulse I/O
Number of output selection
V
sel
Driver voltage selection
CLK
Shift clock input
STB
Latch input
V
0
to V
10
γ-corrected
power supply
INV
Data inversion input
V
DD1
V
DD2
V
SS1
V
SS2
Logic circuit power supply
Driver circuit power supply
Logic ground
Driver ground
Caution
Be sure to turn on power in the order V
DD1
, logic input, V
DD2
, and gray scale power (V
0
to V
10
), and
turn off power in the reverse order, to prevent the
µ
PD16640B from being damaged by latchup. Be
sure to observe this power sequence even during a transition period.
4
Data Sheet S12581EJ1V0DS00
µ
PD16640B
4. RELATION BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE
The 11 major points on the
γ
characteristic curve of the LCD panel are arbitrarily set by external power supplies V
0
through V
10
. If the display data is 00H or 3FH, gray scale voltage V
0
or V
10
is output. If the display data is in the
range 01H to 3EH, the high-order 3 bits select an external powers pair V
n+1
, V
n
. The low-order 3 bits evenly divide
the range of V
n+1
to V
n
into eight segments by means of D/A conversion (however, the ranges from V
9
to V
8
and from
V
2
to V
1
are divided into seven segments) to output a 64-grayscale voltage.
D
X5
(MSB)
D
X4
D
X3
D
X2
D
X1
D
X0
(LSB)
High-order 3 bits :
γ-corrected
power selected
(V
n
, V
n+1
)
Low-order 3 bits : 3-bit D/A
(range V
n
to V
n+1
is divided into 7 or 8 segnents)
D
X5
0
0
0
0
1
1
1
1
D
X4
0
0
1
1
0
0
1
1
D
X3
0
1
0
1
0
1
0
1
V
n
to V
n+1
V
1
to V
2
V
2
to V
3
V
3
to V
4
V
4
to V
5
V
5
to V
6
V
6
to V
7
V
7
to V
8
V
8
to V
9
V
n
1
2
3
4
5
6
7
8
000 001 010 011 100 101 110 111
D
X2
to D
X0
V
n+1
Figure4−1. Relationship between Input Data and
γ-corrected
Voltage
V
DD2
0.1 V
V
0
V
1
V
2
Gray-scale supply specified
by 00H
7 segments
8 segments
V
3
8 segments
V
4
8 segments
V
5
8 segments
V
6
8 segments
V
7
8 segments
V
8
7 segments
V
9
V
10
0.1 V
V
SS2
Gray-scale supply specified
by 3FH
Input data (HEX)
Data Sheet S12581EJ1V0DS00
5
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