4, 8 MEG x 64
NONBUFFERED DRAM DIMMs
DRAM
MODULE
FEATURES
• JEDEC-standard ECC pinout in a 168-pin, dual in-line
memory module (DIMM)
• 32MB (4 Meg x 64) and 64MB (8 Meg x 64)
• Nonbuffered
• High-performance CMOS silicon-gate process
• Single +3.3V
±0.3V
power supply
• All inputs, outputs and clocks are LVTTL-compatible
• 4,096-cycle CAS#-BEFORE-RAS# (CBR) refresh
distributed across 64ms
• FAST-PAGE-MODE (FPM) or Extended Data-Out
(EDO) PAGE MODE access cycles
• Serial presence-detect (SPD)
MT4LDT464A (X), MT8LDT864A (X)
For the latest full-length data sheet, please refer to the
Micron Web site:
www.micron.com/mti/msp/html/
datasheet.html
PIN ASSIGNMENT (Front View)
168-Pin DIMM
(H-10; 32MB), (H-11; 64MB)
OPTIONS
• Package
168-pin DIMM (gold)
• Timing
50ns access
60ns access
• Access Cycle
FAST PAGE MODE
EDO PAGE MODE
MARKING
G
-5
-6
None
X
KEY TIMING PARAMETERS
EDO Operating Mode
SPEED
-5
-6
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
CAS
84ns
104ns
50ns
60ns
20ns
25ns
25ns
30ns
13ns
15ns
8ns
10ns
FPM Operating Mode
SPEED
-5
-6
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
RP
90ns
110ns
50ns
60ns
30ns
35ns
25ns
30ns
13ns
15ns
30ns
40ns
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
SYMBOL
V
SS
DQ0
DQ1
DQ2
DQ3
V
DD
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
DD
DQ14
DQ15
NC
NC
V
SS
NC
NC
V
DD
WE0#
CAS0#
CAS1#
RAS0#
OE0#
V
SS
A0
A2
A4
A6
A8
A10
NC (A12)
V
DD
V
DD
RFU
PIN
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
SYMBOL
V
SS
OE2#
RAS2#
CAS2#
CAS3#
WE2#
V
DD
NC
NC
NC
NC
V
SS
DQ16
DQ17
DQ18
DQ19
V
DD
DQ20
NC
RFU
NC
V
SS
DQ21
DQ22
DQ23
V
SS
DQ24
DQ25
DQ26
DQ27
V
DD
DQ28
DQ29
DQ30
DQ31
V
SS
NC
NC
NC
SDA
SCL
V
DD
PIN
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
SYMBOL
V
SS
DQ32
DQ33
DQ34
DQ35
V
DD
DQ36
DQ37
DQ38
DQ39
DQ40
V
SS
DQ41
DQ42
DQ43
DQ44
DQ45
V
DD
DQ46
DQ47
NC
NC
V
SS
NC
NC
V
DD
RFU
CAS4#
CAS5#
RAS1#
RFU
V
SS
A1
A3
A5
A7
A9
A11
NC (A13)
V
DD
RFU
RFU
PIN
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
SYMBOL
V
SS
RFU
RAS3#
CAS6#
CAS7#
RFU
V
DD
NC
NC
NC
NC
V
SS
DQ48
DQ49
DQ50
DQ51
V
DD
DQ52
NC
RFU
NC
V
SS
DQ53
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
DQ59
V
DD
DQ60
DQ61
DQ62
DQ63
V
SS
NC
NC
SA0
SA1
SA2
V
DD
NOTE:
Pin symbols in parentheses are not used on these modules but may be
used for other modules in this product family. They are for reference only.
4, 8 Meg x 64 Nonbuffered DRAM DIMMs
DM88.p65 – Rev. 2/99
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999,
Micron Technology, Inc.
Micron is a registered trademark of Micron Technology, Inc.
4, 8 MEG x 64
NONBUFFERED DRAM DIMMs
PART NUMBERS
EDO Operating Mode
PART NUMBER
MT4LDT464AG-5 X
MT4LDT464AG-6 X
MT8LDT864AG-5 X
MT8LDT864AG-6 X
CONFIGURATION
4 Meg x 64
4 Meg x 64
8 Meg x 64
8 Meg x 64
SPEED
50ns
60ns
50ns
60ns
FPM Operating Mode
PART NUMBER
MT4LDT464AG-5
MT4LDT464AG-6
MT8LDT864AG-5
MT8LDT864AG-6
CONFIGURATION
4 Meg x 64
4 Meg x 64
8 Meg x 64
8 Meg x 64
SPEED
50ns
60ns
50ns
60ns
GENERAL DESCRIPTION
The MT4LDT464A (X) and MT8LDT864A (X) are ran-
domly accessed 32MB and 64MB memories organized in a
x64 configuration. They are specially processed to operate
from 3V to 3.6V for low-voltage memory systems.
During READ or WRITE cycles, each bit is uniquely
addressed through the 22 address bits, which are entered 12
bits (A0 -A11) at RAS# time and 10 bits (A0-A9) at CAS#
time.
READ and WRITE cycles are selected with the WE#
input. A logic HIGH on WE# dictates read mode, while a
logic LOW on WE# dictates write mode. During a WRITE
cycle, data-in (D) is latched by the falling edge of WE# or
CAS#, whichever occurs last. An EARLY WRITE occurs
when WE# is taken LOW prior to CAS# falling. A LATE
WRITE or READ-MODIFY-WRITE occurs when WE# falls
after CAS# is taken LOW. During EARLY WRITE cycles,
the data-outputs (Q) will remain High-Z regardless of the
state of OE#. During LATE WRITE or READ-MODIFY-
WRITE cycles, OE# must be taken HIGH to disable the
data-outputs prior to applying input data. If a LATE WRITE
or READ-MODIFY-WRITE is attempted while keeping OE#
LOW, no WRITE will occur, and the data-outputs will drive
read data from the accessed location.
data going invalid. This elimination of CAS# output control
provides for pipelined READs.
FAST-PAGE-MODE modules have traditionally turned
the output buffers off (High-Z) with the rising edge of
CAS#. EDO-PAGE-MODE DRAMs operate like FAST-
PAGE-MODE DRAMs, except data will remain valid or
become valid after CAS# goes HIGH during READs, pro-
vided RAS# and OE# are held LOW. If OE# is pulsed while
RAS# and CAS# are LOW, data will toggle from valid data
to High-Z and back to the same valid data. If OE# is toggled
or pulsed after CAS# goes HIGH while RAS# remains
LOW, data will transition to and remain High-Z.
During an application, if the DQ outputs are wire OR’d,
OE# must be used to disable idle banks of DRAMs. Alter-
natively, pulsing WE# to the idle banks during CAS# HIGH
time will also tristate the outputs. Independent of OE#
control, the outputs will disable after
t
OFF, which is refer-
enced from the rising edge of RAS# or CAS#, whichever
occurs last. (Refer to the 4 Meg x 16 [MT4LC4M16R6]
DRAM data sheet for additional information on EDO
functionality.)
REFRESH
Returning RAS# and CAS# HIGH terminates a memory
cycle and decreases chip current to a reduced standby level.
Also, the chip is preconditioned for the next cycle during
the RAS# HIGH time. Correct memory cell data is pre-
served by maintaining power and executing any RAS#
cycle (READ, WRITE) or RAS# REFRESH cycle (RAS#-
ONLY, CBR or HIDDEN) so that all combinations of
RAS# addresses (A0-A11) are executed at least every
t
REF,
regardless of sequence. The CBR REFRESH cycle will in-
voke the internal refresh counter for automatic RAS#
addressing.
SERIAL PRESENCE-DETECT OPERATION
This module family incorporates serial presence-detect
(SPD). The SPD function is implemented using a 2,048-bit
EEPROM. This nonvolatile storage device contains 256
bytes. The first 128 bytes can be programmed by Micron to
identify the module type and various DRAM organizations
and timing parameters. The remaining 128 bytes of storage
are available for use by the customer. System READ/
WRITE operations between the master (system logic) and
the slave EEPROM device (DIMM) occur via a standard IIC
bus using the DIMM’s SCL (clock) and SDA (data) signals,
together with SA(2:0), which provide eight unique DIMM/
EEPROM addresses.
EDO PAGE MODE
EDO PAGE MODE is an accelerated FAST-PAGE-MODE
cycle. The primary advantage of EDO is the availability of
data-out even after CAS# goes back HIGH. EDO provides
for CAS# precharge time (
t
CP) to occur without the output
4, 8 Meg x 64 Nonbuffered DRAM DIMMs
DM88.p65 – Rev. 2/99
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999,
Micron Technology, Inc.
4, 8 MEG x 64
NONBUFFERED DRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
MT4LDT464A (X) (32MB)
DQ0-DQ15
DQ16-DQ31
16
16
DQ0-DQ15
DQ0-DQ15
WE#
OE#
WE0#
OE0#
RAS0#
CAS0#
CAS1#
WE#
OE#
RAS#
UCAS#
LCAS#
A0-A11
U1
RAS#
UCAS#
LCAS#
U2
A0-A11
CAS2#
CAS3#
12
12
DQ32-DQ47
12
A0-A11
DQ48-DQ63
16
16
DQ0-DQ15
DQ0-DQ15
WE#
OE#
WE0#
OE0#
RAS0#
CAS4#
CAS5#
WE#
OE#
RAS#
UCAS#
LCAS#
A0-A11
U3
RAS#
UCAS#
LCAS#
U4
A0-A11
CAS6#
CAS7#
12
12
11
SPD
V
DD
SCL
A0
SA0
A1
SA1
A2
SA2
SDA
U1-U4
U1-U4
V
SS
U1-U4 = MT4LC4M16F5 FAST PAGE MODE
U1-U4 = MT4LC4M16R6 EDO PAGE MODE
4, 8 Meg x 64 Nonbuffered DRAM DIMMs
DM88.p65 – Rev. 2/99
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999,
Micron Technology, Inc.
4, 8 MEG x 64
NONBUFFERED DRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
MT8LDT864A (X) (64MB)
DQ0-DQ15
DQ16-DQ31
16
16
DQ0-DQ15
DQ0-DQ15
WE#
OE#
WE0#
OE0#
RAS0#
CAS0#
CAS1#
WE#
OE#
RAS#
UCAS#
LCAS#
A0-A11
U1
RAS#
UCAS#
LCAS#
U2
A0-A11
CAS2#
CAS3#
A0-A11
12
12
DQ32-DQ47
12
DQ48-DQ63
16
16
DQ0-DQ15
DQ0-DQ15
WE#
OE#
WE2#
OE2#
RAS2#
CAS4#
CAS5#
WE#
OE#
RAS#
UCAS#
LCAS#
A0-A11
U3
RAS#
UCAS#
LCAS#
U4
A0-A11
CAS6#
CAS7#
12
12
11
DQ0-DQ15
DQ16-DQ31
16
16
DQ0-DQ15
WE#
OE#
WE#
OE#
U5
RAS#
DQ0-DQ15
RAS1#
RAS#
UCAS#
LCAS#
U6
UCAS#
LCAS#
A0-A11
A0-A11
12
11
DQ32-DQ47
12
DQ48-DQ63
16
16
DQ0-DQ15
WE#
OE#
WE#
OE#
U7
RAS#
DQ0-DQ15
RAS3#
RAS#
UCAS#
LCAS#
U8
UCAS#
LCAS#
A0-A11
A0-A11
12
12
11
SPD
V
DD
SCL
A0
SA0
A1
SA1
A2
SA2
SDA
U1-U8
U1-U8
V
SS
U1-U8 = MT4LC4M16F5 FAST PAGE MODE
U1-U8 = MT4LC4M16R6 EDO PAGE MODE
4, 8 Meg x 64 Nonbuffered DRAM DIMMs
DM88.p65 – Rev. 2/99
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999,
Micron Technology, Inc.
4, 8 MEG x 64
NONBUFFERED DRAM DIMMs
PIN DESCRIPTIONS
PIN NUMBERS
30, 45, 114, 129
SYMBOL
RAS0#-RAS3#
TYPE
Input
DESCRIPTION
Row-Address Strobe: RAS# is used to clock-in the row-
address bits. Two RAS# inputs allow for one x64 bank or
two x32 banks.
Column-Address Strobe: CAS# is used to clock-in the
column-address bits, enable the DRAM output buffers
and strobe the data inputs on WRITE cycles.
Write Enable: WE# is the READ/WRITE control for the
DQ pins. If WE# is LOW prior to CAS# going LOW, the
access is an EARLY WRITE cycle. If WE# is HIGH while
CAS# is LOW, the access is a READ cycle, provided OE#
is also LOW. If WE# goes LOW after CAS# goes LOW,
then the cycle is a LATE WRITE cycle. A LATE WRITE
cycle is generally used in conjunction with a READ cycle
to form a READ-MODIFY-WRITE cycle.
Output Enable: OE# is the input/output control for the DQ
pins. These signals may be driven, allowing LATE WRITE
cycles.
Address Inputs: These inputs are multiplexed and clocked
by RAS# and CAS#.
Data I/O: For WRITE cycles, DQ0-DQ63 act as inputs to
the addressed DRAM location. For READ access cycles,
DQ0-DQ63 act as outputs for the addressed DRAM
location.
28, 29, 46, 47, 112, 113, CAS0#-CAS7#
130, 131
27, 48
WE0#, WE2#
Input
Input
31, 44
OE0#, OE2#
Input
33-38, 117-122
2-5, 7-11, 13-17, 19, 20,
55-58, 60, 65-67, 69-72,
74-77, 86-89, 91-95,
97-101, 103, 104,
139-142, 144, 149-151,
153-156, 158-161
42, 62, 111, 115,
125-126, 128, 132, 146
6, 18, 26, 40, 41, 49, 59,
73, 84, 90, 102, 110,
124, 133, 143, 157, 168
1, 12, 23, 32, 43, 54, 64,
68, 78, 85, 96, 107, 116,
127, 138, 148, 152, 162
82
A0-A11
DQ0-DQ63
Input
Input/
Output
RFU
V
DD
–
Supply
Reserved for Future Use: These pins should be left
unconnected.
Power Supply: +3.3V
±0.3V.
V
SS
Supply
Ground.
SDA
Input/Output
Serial Presence-Detect Data. SDA is a bidirectional pin
used to transfer addresses and data into and data out of
the presence-detect portion of the module.
Serial Clock for Presence-Detect. SCL is used to
synchronize the presence-detect data transfer to and
from the module.
Presence-Detect Address Inputs. These pins are used to
configure the presence-detect device.
83
SCL
Input
165-167
SA0-SA2
Input
4, 8 Meg x 64 Nonbuffered DRAM DIMMs
DM88.p65 – Rev. 2/99
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999,
Micron Technology, Inc.
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