White Electronic Designs
512K x 32/256K x 32 Dual Array
Synchronous Pipeline Burst NBL SRAM
FEATURES
Fast clock speed: 166, 150, 133, and 100MHz
Fast access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns
Fast OE# access times: 3.5ns, 3.8ns, 4.2ns, and
5.0ns
Single +2.5V ± 5% power supply (V
CC
)
Snooze Mode for reduced-standby power
Individual Byte Write control
Clock-controlled and registered addresses, data
I/Os and control signals
Burst control (interleaved or linear burst)
Packaging:
209-bump BGA package
Low capacitive bus loading
WED2ZLRSP01S
DESCRIPTION
The WED2ZLRSP01S, Dual Independent Array, NBL-
SSRAM device employs high-speed, Low-Power CMOS
silicon and is fabricated using an advanced CMOS process.
WEDC’s 24Mb, Sync Burst SRAM MCP integrates two
totally independent arrays, the first organized as a 512K x
32, and the second a 256K x 32.
All Synchronous inputs pass through registers controlled
by a positive edge triggered, single clock input per array.
The NBL or No Bus Latency Memory provides 100% bus
utilizaton, with no loss of cycles caused by change in modal
operation (Write to Read/Read to Write). All inputs except
for Asynchronous Output Enable and Burst Mode control
are synchronized on the positive or rising edge of Clock.
Burst order control must be tied either HIGH or LOW, Write
cycles are internally self-timed, and writes are initiated on
the rising edge of clock. This feature eliminates the need
for complex off-chip write pulse generation and proved
increased timing flexibility for incoming signals.
PIN CONFIGURATION
(TOP VIEW)
1
Vss
NC
A_ADR
A_ADR
A_ADR
A_ADR
A_ADR
NC
Vss
Vss
Vss
NC
B_ADR
B_ADR
B_ADR
B_ADR
B_ADR
NC
Vss
2
A_DATb
0
A_DATb
4
A_ADR
Vss
A_CK
Vss
A_ADR
A_DATc
0
A_DATc
4
Vss
B_DATb
0
B_DATb
4
B_ADR
Vss
B_CK
Vss
NC
B_DATc
4
B_DATc
0
3
A_DATb
1
A_DATb
5
A_OE#
A_CKE#
A_GWE#
A_CS
2
#
A_CS
1
#
A_DATc
1
A_DATc
5
Vss
B_DATb
1
B_DATb
5
B_OE#
B_CKE#
B_GWE#
B_CS
2
#
B_CS
1
#
B_DATc
5
B_DATc
1
4
A_DATb
2
A_DATb
6
A_ADV
Vcc
Vcc
Vcc
A_CS
2
A_DATc
2
A_DATc
6
Vss
B_DATb
2
B_DATb
6
B_ADV
Vcc
Vcc
Vcc
B_CS
2
B_DATc
6
B_DATc
2
5
A_DATb
3
A_DATb
7
A_BWEb
Vcc
Vcc
Vcc
A_BWEc
A_DATc
3
A_DATc
7
Vss
B_DAT
3
B_DAT
7
B_BWEb
Vcc
Vcc
Vcc
B_BWE
c
B_DATc
7
B_DATc
3
6
Vss
Vss
Vss
Vcc
Vcc
Vcc
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vcc
Vcc
Vcc
Vss
Vss
Vss
7
A_DATa
0
A_DATa
4
A_BWEa
Vcc
Vcc
Vcc
A_BWEd
A_DATd
0
A_DATd
4
Vss
B_DATa
0
B_DATa
4
B_BWEa
Vcc
Vcc
Vcc
B_BWEd
B_DATd
4
B_DATd
0
8
A_DATa
1
A_DATa
5
A_ZZ
Vcc
Vcc
Vcc
A_LBO#
A_DATd
1
A_DATd
5
Vss
B_DATa
1
B_DATa
5
B_ZZ
Vcc
Vcc
Vcc
B_LBO#
B_DATd
5
B_DATd
1
9
A_DATa
2
A_DATa
6
A_ADR
Vcc
Vcc
Vcc
A_ADR
A_DATd
2
A_DATd
6
Vss
B_DATa
2
B_DATa
6
B_ADR
Vcc
Vcc
Vcc
B_ADR
B_DATd
6
B_DATd
2
10
A_DATa
3
A_DATa
7
A_ADR
A_ADR
A_ADR
1
A_ADR
A_ADR
A_DATd
3
A_DATd
7
Vss
B_DATa
3
B_DATa
7
B_ADR
B_ADR
B_ADR
1
B_ADR
B_ADR
B_DATd
7
B_DATd
3
11
Vss
NC
A_ADR
A_ADR
A_ADR
0
A_ADR
A_ADR
NC
Vss
Vss
Vss
NC
B_ADR
B_ADR
B_ADR
0
B_ADR
B_ADR
NC
Vss
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April, 2002
Rev. 0
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
FIG. 1 BLOCK DIAGRAM
A_SA0-18
B_SA0-17
A_DQ0-31
B_DQ0-31
WED2ZLRSP01S
A_LBO#
A_ZZ
A_ADV
A_OE#
A_CKE#
A_WE#
A_CK
A_BWA#
A_BWB#
A_BWC#
A_BWD#
A_CS2#
A_CS2
A_CS1#
LBO#
ZZ
ADV
OE#
CKE#
WE#
CK
BWa#
BWb#
BWc#
BWd#
CS2#
CS2
CS1#
U1
DQ0-31
512K x 32
B_LBO#
B_ZZ
B_ADV
B_OE#
B_CKE#
B_WE#
B_CK
B_BWA#
B_BWB#
B_BWC#
B_BWD#
B_CS2#
B_CS2
B_CS1#
LBO#
ZZ
ADV
OE#
CKE#
WE#
CK
BWa#
BWb#
BWc#
BWd#
CS2#
CS2
CS1#
U2
DQ0-31
256K x 32
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April, 2002
Rev. 0
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White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
FUNCTION DESCRIPTION
The WED2ZLRSP01S is an NBL Dual Array SSRAM
designed to sustain 100% bus bandwidth by eliminating
turnaround cycle when there is transition from Read to
Write, or vice versa. All inputs (with the exception of OE#,
LBO# and ZZ) are synchronized to rising clock edges,
and all features are available on each of the independent
arrays.
All read, write and deselect cycles are initiated by the
ADV input. Subsequent burst addresses can be internally
generated by the burst advance pin (ADV). ADV should
be driven to Low once the device has been deselected in
order to load a new address for next operation.
Clock Enable (CKE#) pin allows the operation of the chip
to be suspended as long as necessary. When CKE# is
high, all synchronous inputs are ignored and the internal
device registers will hold their previous values. NBL
SSRAM latches external address and initiates a cycle
when CKE# and ADV are driven low at the rising edge
of the clock.
Output Enable (OE#) can be used to disable the output
at any given time. Read operation is initiated when at
the rising edge of the clock, the address presented to
the address inputs are latched in the address register,
CKE# is driven low, the write enable input signals WE#
are driven high, and ADV driven low. The internal array is
read between the first rising edge and the second rising
edge of the clock and the data is latched in the output
register. At the second clock edge the data is driven out
of the SRAM. During read operation OE# must be driven
low for the device to drive out the requested data.
WED2ZLRSP01S
Write operation occurs when WE# is driven low at the rising
edge of the clock. BW#[d:a] can be used for byte write
operation. The pipe-lined NBL SSRAM uses a late-late write
cycle to utilize 100% of the bandwidth. At the first rising edge
of the clock, WE and address are registered, and the data
associated with that address is required two cycle later.
Subsequent addresses are generated by ADV High for
the burst access as shown below. The starting point of the
burst seguence is provided by the external address. The
burst address counter wraps around to its initial state upon
completion. The burst sequence is determined by the state
of the LBO# pin. When this pin is low, linear burst sequence
is selected. And when this pin is high, Interleaved burst
sequence is selected.
During normal operation, ZZ must be driven low. When ZZ
is driven high, the SRAM will enter a Power Sleep Mode
after 2 cycles. At this time, internal state of the SRAM is
preserved. When ZZ returns to low, the SRAM operates
after 2 cycles of wake up time.
BURST SEQUENCE TABLE
(Interleaved Burst, LBO# = High)
Case 1
LBO# Pin High
First Address
A
1
0
0
1
1
A
0
0
1
0
1
Case 2
A
1
0
0
1
1
A
0
1
0
1
0
Case 3
A
1
1
1
0
0
A
0
0
1
0
1
Case 4
A
1
1
1
0
0
A
0
1
0
1
0
LBO# Pin High
First Address
(Interleaved Burst, LBO = High)
Case 1
A
1
0
0
1
1
A
0
0
1
0
1
Case 2
A
1
0
1
1
0
A
0
1
0
1
0
Case 3
A
1
1
1
0
0
A
0
0
1
0
1
Case 4
A
1
1
0
0
1
A
0
1
0
1
0
↓
Fourth Address
↓
Fourth Address
NOTE 1: LBO# pin must be tied to High or Low, and Floating State must not be allowed.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April, 2002
Rev. 0
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White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
CEx#
H
X
L
X
L
X
L
X
L
X
X
ADV
L
H
L
H
L
H
L
H
L
H
X
WE#
X
X
H
X
H
X
L
X
L
X
X
BWx#
X
X
X
X
X
X
L
L
H
H
X
OE#
X
X
L
L
H
H
X
X
X
X
X
CKE#
L
L
L
L
L
L
L
L
L
L
H
CK
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
Address Accessed
N/A
N/A
External Address
Next Address
External Address
Next Address
External Address
Next Address
N/A
Next Address
Current Address
WED2ZLRSP01S
Operation
Deselect
Continue Deselect
Begin Burst Read Cycle
Continue Burst Read Cycle
NOP/Dummy Read
Dummy Read
Begin Burst Write Cycle
Continue Burst Write Cycle
NOP/Write Abort
Write Abort
Ignore Clock
NOTES:
1. X means “Don’t Care.”
2. The rising edge of clock is symbolized by (
↑
)
3. A continue deselect cycle can only be entered if a deselect cycle is executed first.
4. WRITE# = L means Write operation in WRITE TRUTH TABLE.
WRITE# = H means Read operation in WRITE TRUTH TABLE.
5. Operation finally depends on status of asynchronous input pins (ZZ and OE#).
6. CEx# refers to the combination of CE
1
#, CE
2
and CE
2
#.
7. Applies to each of the independent arrays.
WRITE TRUTH TABLE
WE#
H
L
L
L
L
L
L
BWa# BWb# BWc# BWd#
X
X
X
X
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
L
L
L
L
H
H
H
H
Operation
Read
Write Byte a
Write Byte b
Write Byte c
Write Byte d
Write All Bytes
Write Abort/NOP
NOTES:
1. X means “Don’t Care.”
2. All inputs in this table must meet setup and hold time around the rising
edge of CK (
↑
).
3. Applies to each of the independent arrays.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April, 2002
Rev. 0
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White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS*
Voltage on Vdd Supply Relative to V
SS
V
IN
(DQx)
V
IN
(Inputs)
Storage Temperature (BGA)
Short Circuit Output Current
WED2ZLRSP01S
-0.3V to +3.6V
-0.3V to +3.6V
-0.3V to +3.6V
-55°C to +125°C
100mA
*Stress greater than those listed under “Absolute Maximum Ratings”: may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating condtions for extended periods may affect reliability.
ELECTRICAL CHARACTERISTICS (0°C ≤ T
A
≤ 70°C)
Description
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Supply Voltage
Symbol
V
IH
V
IL
I
LI
I
LO
V
OH
V
OL
V
CC
Conditions
Min
1.7
-0.3
-5
-5
2.0
---
2.375
Max
V
CC
+0.3
0.7
5
5
---
0.4
2.625
Units
V
V
µA
µA
V
V
V
Notes
1
1
2
1
1
1
0V ≤ V
IN
≤ V
CC
Output(s) Disabled, 0V ≤ V
IN
≤ V
CC
I
OH
= -1.0mA
I
OL
= 1.0mA
NOTES:
1. All voltages referenced to V
SS
(GND)
2. ZZ pin has an internal pull-up, and input leakage is higher.
DC CHARACTERISTICS
Description
Power Supply
Current: Operating
Power Supply
Current: Standby
Power Supply
Current: Current
Clock Running
Standby Current
Symbol
I
DD
I
SB2
Conditions
Device Selected; All Inputs ≤ V
IL
or ≥ V
IH
; Cycle
Time = t
CYC
MIN; V
CC
= MAX; Output Open
Device Deselected; V
CC
= MAX; All Inputs ≤ V
SS
+ 0.2
or V
CC
- 0.2; All Inputs Static; CK Frequency = 0;
ZZ ≤ V
IL
Device Selected; All Inputs ≤ V
IL
or ≥ V
IH
; Cycle
Time =t
CYC
MIN; V
CC
= MAX; Output Open;
ZZ ≥ V
CC
- 0.2V
Device Deselected; V
CC
= MAX; All Inputs
≤ V
SS
+ 0.2 or V
CC
- 0.2; Cycle Time = t
CYC
MIN; ZZ ≤ V
IL
Typ
166
MHz
650
30
60
150
MHz
600
60
133
MHz
560
60
100
MHz
500
60
Units
mA
mA
Notes
1, 2
2
I
SB3
20
40
40
40
40
mA
2
I
SB4
140
120
100
80
mA
2
NOTES:
1. I
DD
is specified with no output current and increases with faster cycle times. I
DD
increases with faster cycle times and greater output loading.
2. Typical values are measured at 2.5V, 25°C, and 10ns cycle time.
BGA CAPACITANCE
Description
Control Input Capacitance
Input/Output Capacitance (DQ)
Address Capacitance
Clock Capacitance
Symbol
C
I
C
O
C
A
C
CK
Conditions
T
A
= 25°C; f = 1MH
Z
T
A
= 25°C; f = 1MH
Z
T
A
= 25°C; f = 1MH
Z
T
A
= 25°C; f = 1MH
Z
Typ
5
6
5
3
Max
7
8
7
5
Units
pF
pF
pF
pF
Notes
1
1
1
1
NOTES:
1. This parameter is sampled.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April, 2002
Rev. 0
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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