WED2ZLRSP01S50BC datasheet, PDF

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WED2ZLRSP01S50BC: DescriptionSRAM Module, 512KX32, 5ns, CMOS, PBGA209, PLASTIC, BGA-209; Categorystorage storage; File Size351KB，13 Pages; ManufacturerWhite Electronic Designs Corporation; Websitehttp://www.wedc.com/

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WED2ZLRSP01S50BC Overview

SRAM Module, 512KX32, 5ns, CMOS, PBGA209, PLASTIC, BGA-209

WED2ZLRSP01S50BC Parametric

Parameter Name	Attribute value
Maker	White Electronic Designs Corporation
package instruction	PLASTIC, BGA-209
Reach Compliance Code	unknown
Maximum access time	5 ns
JESD-30 code	R-PBGA-B209
memory density	16777216 bit
Memory IC Type	SRAM MODULE
memory width	32
Number of functions	1
Number of terminals	209
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	512KX32
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Maximum supply voltage (Vsup)	2.625 V
Minimum supply voltage (Vsup)	2.375 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal location	BOTTOM
Base Number Matches	1

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White Electronic Designs

512K x 32/256K x 32 Dual Array

Synchronous Pipeline Burst NBL SRAM

FEATURES

Fast clock speed: 166, 150, 133, and 100MHz

Fast access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns

Fast OE# access times: 3.5ns, 3.8ns, 4.2ns, and

5.0ns

Single +2.5V ± 5% power supply (V

)

Snooze Mode for reduced-standby power

Individual Byte Write control

Clock-controlled and registered addresses, data

I/Os and control signals

Burst control (interleaved or linear burst)

Packaging:

209-bump BGA package

Low capacitive bus loading

WED2ZLRSP01S

DESCRIPTION

The WED2ZLRSP01S, Dual Independent Array, NBL-

SSRAM device employs high-speed, Low-Power CMOS

silicon and is fabricated using an advanced CMOS process.

WEDC’s 24Mb, Sync Burst SRAM MCP integrates two

totally independent arrays, the ﬁrst organized as a 512K x

32, and the second a 256K x 32.

All Synchronous inputs pass through registers controlled

by a positive edge triggered, single clock input per array.

The NBL or No Bus Latency Memory provides 100% bus

utilizaton, with no loss of cycles caused by change in modal

operation (Write to Read/Read to Write). All inputs except

for Asynchronous Output Enable and Burst Mode control

are synchronized on the positive or rising edge of Clock.

Burst order control must be tied either HIGH or LOW, Write

cycles are internally self-timed, and writes are initiated on

the rising edge of clock. This feature eliminates the need

for complex off-chip write pulse generation and proved

increased timing ﬂexibility for incoming signals.

PIN CONFIGURATION

(TOP VIEW)

Vss

A_ADR

Vss

B_ADR

Vss

A_DATb

A_ADR

Vss

A_CK

Vss

A_ADR

A_DATc

Vss

B_DATb

B_ADR

Vss

B_CK

Vss

B_DATc

A_DATb

A_OE#

A_CKE#

A_GWE#

A_CS

A_DATc

Vss

B_DATb

B_OE#

B_CKE#

B_GWE#

B_CS

B_DATc

A_DATb

A_ADV

Vcc

A_CS

A_DATc

Vss

B_DATb

B_ADV

Vcc

B_CS

B_DATc

A_DATb

A_BWEb

Vcc

A_BWEc

A_DATc

Vss

B_DAT

B_BWEb

Vcc

B_BWE

B_DATc

Vss

Vcc

Vss

Vcc

Vss

A_DATa

A_BWEa

Vcc

A_BWEd

A_DATd

Vss

B_DATa

B_BWEa

Vcc

B_BWEd

B_DATd

A_DATa

A_ZZ

Vcc

A_LBO#

A_DATd

Vss

B_DATa

B_ZZ

Vcc

B_LBO#

B_DATd

A_DATa

A_ADR

Vcc

A_ADR

A_DATd

Vss

B_DATa

B_ADR

Vcc

B_ADR

B_DATd

A_DATa

A_ADR

A_DATd

Vss

B_DATa

B_ADR

B_DATd

Vss

A_ADR

Vss

B_ADR

Vss

White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice.

April, 2002

Rev. 0

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

WED2ZLRSP01S50BC Related Products

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Description	SRAM Module, 512KX32, 5ns, CMOS, PBGA209, PLASTIC, BGA-209	SRAM Module, 512KX32, 3.8ns, CMOS, PBGA209, PLASTIC, BGA-209	SRAM Module, 512KX32, 5ns, CMOS, PBGA209, PLASTIC, BGA-209	SRAM Module, 512KX32, 3.8ns, CMOS, PBGA209, PLASTIC, BGA-209	SRAM Module, 512KX32, 4.2ns, CMOS, PBGA209, PLASTIC, BGA-209	SRAM Module, 512KX32, 4.2ns, CMOS, PBGA209, PLASTIC, BGA-209	SRAM Module, 512KX32, 3.5ns, CMOS, PBGA209, PLASTIC, BGA-209
Maker	White Electronic Designs Corporation	White Electronic Designs Corporation	White Electronic Designs Corporation	White Electronic Designs Corporation	White Electronic Designs Corporation	White Electronic Designs Corporation	White Electronic Designs Corporation
package instruction	PLASTIC, BGA-209	PLASTIC, BGA-209	PLASTIC, BGA-209	PLASTIC, BGA-209	PLASTIC, BGA-209	PLASTIC, BGA-209	PLASTIC, BGA-209
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown
Maximum access time	5 ns	3.8 ns	5 ns	3.8 ns	4.2 ns	4.2 ns	3.5 ns
JESD-30 code	R-PBGA-B209	R-PBGA-B209	R-PBGA-B209	R-PBGA-B209	R-PBGA-B209	R-PBGA-B209	R-PBGA-B209
memory density	16777216 bit	16777216 bit	16777216 bit	16777216 bit	16777216 bit	16777216 bit	16777216 bit
Memory IC Type	SRAM MODULE	SRAM MODULE	SRAM MODULE	SRAM MODULE	SRAM MODULE	SRAM MODULE	SRAM MODULE
memory width	32	32	32	32	32	32	32
Number of functions	1	1	1	1	1	1	1
Number of terminals	209	209	209	209	209	209	209
word count	524288 words	524288 words	524288 words	524288 words	524288 words	524288 words	524288 words
character code	512000	512000	512000	512000	512000	512000	512000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	85 °C	85 °C	70 °C	85 °C	70 °C	70 °C
organize	512KX32	512KX32	512KX32	512KX32	512KX32	512KX32	512KX32
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	BGA	BGA	BGA	BGA	BGA	BGA
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum supply voltage (Vsup)	2.625 V	2.625 V	2.625 V	2.625 V	2.625 V	2.625 V	2.625 V
Minimum supply voltage (Vsup)	2.375 V	2.375 V	2.375 V	2.375 V	2.375 V	2.375 V	2.375 V
Nominal supply voltage (Vsup)	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V
surface mount	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	INDUSTRIAL	INDUSTRIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL
Terminal form	BALL	BALL	BALL	BALL	BALL	BALL	BALL
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Base Number Matches	1	1	1	1	1	1	1

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