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BD3532EFV-TR

Description
Terminator Support Circuit, PDSO20, ROHS COMPLIANT, HTSSOP-20
CategoryAnalog mixed-signal IC    Drivers and interfaces   
File Size674KB,17 Pages
ManufacturerROHM Semiconductor
Websitehttps://www.rohm.com/
Download Datasheet Parametric View All

BD3532EFV-TR Overview

Terminator Support Circuit, PDSO20, ROHS COMPLIANT, HTSSOP-20

BD3532EFV-TR Parametric

Parameter NameAttribute value
MakerROHM Semiconductor
Parts packaging codeTSSOP
package instructionROHS COMPLIANT, HTSSOP-20
Contacts20
Reach Compliance Codecompliant
ECCN codeEAR99
Differential outputNO
Interface integrated circuit typeBUS TERMINATOR SUPPORT CIRCUIT
JESD-30 codeR-PDSO-G20
length6.5 mm
Number of functions1
Number of terminals20
Maximum operating temperature100 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeVSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH
Maximum seat height1 mm
Maximum supply voltage5.5 V
Minimum supply voltage4.3 V
Nominal supply voltage5 V
surface mountYES
Temperature levelINDUSTRIAL
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
width4.4 mm
Base Number Matches1
TECHNICAL NOTE
High-performance Regulator IC Series for PCs
Termination Regulators
for DDR-SDRAMs
BD3533F/FVM/EKN(1A),BD3531F(1.5A),BD3532F/EFV/KN(3A)
Description
BD3533/31/32 is a termination regulator compatible with JEDEC DDR-SDRAM, which functions as a linear power supply
incorporating an N-channel MOSFET and provides a sink/source current capability up to 1A, 1.5A, and 3A respectively. A
built-in high-speed OP-AMP specially designed offers an excellent transient response. Requires 3.3 volts or 5.0 volts as a
bias power supply to drive the N-channel MOSFET. Has an independent reference voltage input pin (VDDQ) and an
independent feedback pin (VTTS) to maintain the accuracy in voltage required by JEDEC, and offers an excellent output
voltage accuracy and load regulation. Also has a reference power supply output pin (VREF) for DDR-SDRAM or a
memory controller. When EN pin turns to “Low”, VTT output becomes “Hi-Z” while VREF output is kept unchanged,
compatible with “Self Refresh” state of DDR-SDRAM.
Features
1) Incorporates a push-pull power supply for termination (VTT)
2) Incorporates a reference voltage circuit (VREF)
3) Incorporates an enabler
4) Incorporates an undervoltage lockout (UVLO)
5). Employs SOP8 package
6) Employs MSOP8 package
7) Employs HQFN20V package
8) Employs HTSSOP-B20 package
9) Employs VQFN28V package
10) Incorporates a thermal shutdown protector (TSD)
11) Operates with input voltage from 2.7 to 5.5 volts
12) Compatible with Dual Channel (DDR-II)
Use
Power supply for DDR I/II - SDRAM
●Line
up
Parameter
Output Current
Vcc Range
Soft Start Function
Temperature
Package
BD3533F/FVM/EKN
±1.0A
2.7V½5.5V
-20½100℃
SOP8/MSOP8/HQFN20V
BD3531F
±1.5A
4.5V½5.5V
×
-10½100℃
SOP8
BD3532F/EFV/KN
±3A
4.3½5.5V
-40½100℃
SOP8/HTSSOP-B20/VQFN28
Oct. 2008
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