256Kx4 Bit (with OE) High Speed Static RAM(3.3V Operating), Revolutionary Pin out.
Revision History
Rev No.
Rev. 0.0
Rev.1.0
History
Initial release with Design Target.
Release to Preliminary Data Sheet.
1.1. Replace Design Target to Preliminary.
Release to Final Data Sheet.
2.1. Delete Preliminary.
2.2. Delete L-version.
2.3. Delete Data Retention Characteristics and Waveform.
2.4. Delete Industrial Temperature Range Part.
2.5. Delete TSOP2 Package.
2.6. Add Capacitive load of the test environment in A.C test load.
2.7. Change D.C characteristics.
Previous spec.
Changed spec.
Items
(8/10/12ns part)
(8/10/12ns part)
I
CC
150/140/130mA
150/145/140mA
I
SB
30mA
50mA
Draft Data
Apr. 1st, 1997
Jun. 1st, 1997
Feb. 25th, 1998
Rev.2.0
Remark
Design Target
Preliminary
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Rev 2.0
February 1998
K6R1004V1B-C
FEATURES
• Fast Access Time 8,10,12ns(Max.)
• Low Power Dissipation
Standby (TTL)
: 50mA(Max.)
(CMOS) : 5mA(Max.)
Operating K6R1004V1B-8 : 150mA(Max.)
K6R1004V1B-10 : 145mA(Max.)
K6R1004V1B-12 : 140mA(Max.)
• Single 3.3±0.3V Power Supply
• TTL Compatible Inputs and Outputs
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• Center Power/Ground Pin Configuration
• Standard Pin Configuration
K6R1004V1B-J : 32-SOJ-400
Preliminary
PRELIMINARY
CMOS SRAM
256K x 4 Bit (with OE)High-Speed CMOS Static RAM(3.3V Operating)
GENERAL DESCRIPTION
The K6R1004V1B is a 1,048,576-bit high-speed Static Random
Access Memory organized as 262,144 words by 4 bits. The
K6R1004V1B uses 4 common input and output lines and has
an output enable pin which operates faster than address
access time at read cycle. The device is fabricated using SAM-
SUNG′s advanced CMOS process and designed for high-
speed circuit technology. It is particularly well suited for use in
high-density
high-speed
system
applications.
The
K6R1004V1B is packaged in a 400 mil 32-pin plastic SOJ.
PIN CONFIGURATION
(Top View)
N.C
A
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 A
17
31 A
16
30 A
15
29 A
14
28 A
13
27
OE
FUNCTIONAL BLOCK DIAGRAM
A
1
A
2
A
3
CLK. Gen.
Pre-Charge Circuit
CS
I/O
1
Vcc
26 I/O
4
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
SOJ
25 Vss
24 Vcc
23 I/O
3
22 A
12
21 A
11
20 A
10
19
18
A
9
A
8
Vss
Row Select
I/O
2
Memory Array
256 Rows
1024x4 Columns
WE
A
4
A
5
A
6
A
7
I/O
1
~I/O
4
Data
Cont.
CLK
Gen.
I/O Circuit &
Column Select
N.C
17 N.C
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
PIN FUNCTION
Pin Name
A
0
- A
17
Pin Function
Address Inputs
Write Enable
Chip Select
Output Enable
Data Inputs/Outputs
Power(+3.3V)
Ground
No Connection
CS
WE
OE
WE
CS
OE
I/O
1
~ I/O
4
V
CC
V
SS
N.C
-2-
Rev 2.0
February 1998
K6R1004V1B-C
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on Any Pin Relative to V
SS
Voltage on V
CC
Supply Relative to V
SS
Power Dissipation
Storage Temperature
Operating Temperature
Symbol
V
IN
, V
OUT
V
CC
P
D
T
STG
T
A
Rating
-0.5 to 4.6
-0.5 to 4.6
1.0
-65 to 150
0 to 70
Preliminary
PRELIMINARY
CMOS SRAM
Unit
V
V
W
°C
°C
*
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress ating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(T
A
=0 to 70°C)
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min
3.0
0
2.0
-0.3*
Typ
3.3
0
-
-
Max
3.6
0
V
CC
+ 0.3**
0.8
Unit
V
V
V
V
* V
IL
(Min)=-2.0V a.c(Pulse Width
≤
6ns) for I
≤
20mA.
** V
IH
(Max)=V
CC
+ 2.0V a.c (Pulse Width
≤
6ns) for I
≤
20mA.
DC AND OPERATING CHARACTERISTICS
(T
A
=0 to 70°C, Vcc=3.3±0.3V, unless otherwise specified
)
Parameter
Input Leakage Current
Output Leakage Current
Operating Current
Symbol
I
LI
I
LO
I
CC
Test Conditions
V
IN
=V
SS
to V
CC
CS=V
IH
or OE=V
IH
or WE=V
IL
V
OUT
=V
SS
to V
CC
Min. Cycle, 100% Duty
CS=V
IL,
V
IN
=V
IH
or V
IL,
I
OUT
=0mA
Min. Cycle, CS=V
IH
f=0MHz, CS≥V
CC
-0.2V,
V
IN
≥V
CC
-0.2V or V
IN
≤0.2V
I
OL
=8mA
I
OH
=-4mA
8ns
10ns
12ns
Standby Current
I
SB
I
SB1
Output Low Voltage Level
Output High Voltage Level
V
OL
V
OH
Min
-2
-2
-
-
-
-
-
-
2.4
Max
2
2
150
145
140
50
5
0.4
-
V
V
mA
Unit
µA
µA
mA
CAPACITANCE*
(T
A
=25°C, f=1.0MHz)
Item
Input/Output Capacitance
Input Capacitance
* Capacitance is sampled and not 100% tested.
Symbol
C
I/O
C
IN
Test Conditions
V
I/O
=0V
V
IN
=0V
MIN
-
-
Max
8
6
Unit
pF
pF
-3-
Rev 2.0
February 1998
K6R1004V1B-C
AC CHARACTERISTICS
(T
A
=0 to 70°C, V
CC
=3.3±0.3V, unless otherwise noted.)
TEST CONDITIONS
Parameter
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Reference Levels
Output Loads
Value
0V to 3V
3ns
1.5V
See below
Preliminary
PRELIMINARY
CMOS SRAM
Output Loads(A)
Output Loads(B)
for t
HZ
, t
LZ
, t
WHZ
, t
OW
, t
OLZ
& t
OHZ
R
L
= 50Ω
+3.3V
D
OUT
V
L
= 1.5V
Z
O
= 50Ω
30pF*
D
OUT
353Ω
319Ω
5pF*
* Capacitive Load consists of all components of the
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