ICX282AQF
Diagonal 11mm (Type 2/3) Frame Readout CCD Image Sensor with Square Pixel for Color Cameras
Description
The ICX282AQF is a diagonal 11mm (Type 2/3)
interline CCD solid-state image sensor with a square
pixel array and 5.07M effective pixels. Frame readout
allows all pixels' signals to be output independently
within approximately 1/3.75 second. In addition, output
is possible using various addition and pulse elimination
methods. This chip features an electronic shutter with
variable charge-storage time. Adoption of a design
specially suited for frame readout ensures a saturation
signal level equivalent to that when using field readout.
High resolution and high color reproducibility are
achieved through the use of R, G, B primary color
mosaic filters as the color filters. Further, high
sensitivity and low dark current are achieved through
the adoption of Super HAD CCD technology.
This chip is suitable for applications such as
electronic still cameras, PC input cameras, etc.
24 pin SOP (Plastic)
Features
•
High horizontal and vertical resolution
•
Supports 10 types of readout modes
Frame readout mode, 2× speed mode (1), 2× speed mode (2), 8× speed mode,
center scan mode (1), center scan mode (2), center scan mode (3),
center scan mode (4), AF mode (1), AF mode (2)
•
Square pixel
•
Horizontal drive frequency: 22.5MHz
•
No voltage adjustments (reset gate and substrate bias are not adjusted.)
•
R, G, B primary color mosaic filters on chip
•
High sensitivity, low dark current, excellent anti-blooming characteristics
•
Continuous variable-speed shutter
•
Horizontal register, reset gate: 3.3V drive
V
•
24-pin high-precision plastic package
Pin 1
2
Device Structure
•
Interline CCD image sensor
12
•
Image size:
Diagonal 11mm (Type 2/3)
58
H
Pin 13
•
Total number of pixels:
2658 (H)
×
1970 (V) approx. 5.24M pixels
•
Number of effective pixels: 2588 (H)
×
1960 (V) approx. 5.07M pixels
•
Number of active pixels: 2580 (H)
×
1944 (V) approx. 5.02M pixels
Optical black position
•
Number of recommended recording pixels:
(Top View)
2560 (H)
×
1920 (V) approx. 4.92M pixels
•
Chip size:
9.74mm (H)
×
7.96mm (V)
•
Unit cell size:
3.4µm (H)
×
3.4µm (V)
Horizontal (H) direction: Front 12 pixels, rear 58 pixels
•
Optical black:
Vertical (V) direction:
Front 8 pixels, rear 2 pixels
•
Number of dummy bits:
Horizontal 28
Vertical 1 (even fields only)
•
Substrate material:
Silicon
8
∗
Super HAD CCD is a registered trademark of Sony Corporation. Super HAD CCD is a CCD that drastically improves sensitivity by introducing
newly developed semiconductor technology by Sony Corporation into Sony's high-performance HAD (Hole-Accumulation Diode) sensor.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E00Z39B37
ICX282AQF
GND
GND
Block Diagram and Pin Configuration
(Top View)
Vφ
1C
Vφ
3C
Vφ
1B
Vφ
1A
Vφ
3B
Vφ
3A
Vφ
2
12
11
10
9
8
7
6
5
4
3
2
Gb
R
Vertical register
B
Gr
B
Gr
B
Gr
B
Gr
Gb
R
Gb
R
Gb
R
Gb
R
B
Gr
B
Gr
B
Gr
B
Gr
Note)
Gb
R
Gb
R
Gb
R
Horizontal register
Vφ
4
NC
NC
1
Note)
13
V
OUT
: Photo sensor
14
V
DD
15
φRG
16
Hφ
2B
17
Hφ
1B
18
GND
19
NC
20
φSUB
21
C
SUB
22
V
L
23
Hφ
1A
24
Hφ
2A
Pin Description
Pin No. Symbol
1
2
3
4
5
6
7
8
9
10
11
12
Vφ
4
Vφ
3A
Vφ
3B
Vφ
3C
Vφ
2
NC
NC
Vφ
1A
Vφ
1B
Vφ
1C
GND
GND
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
GND
GND
Description
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Pin No.
13
14
15
16
17
18
19
20
21
22
23
24
Symbol
V
OUT
V
DD
φRG
Hφ
2B
Hφ
1B
GND
NC
φSUB
C
SUB
V
L
Hφ
1A
Hφ
2A
Substrate clock
Substrate bias
∗
1
Protective transistor bias
Horizontal register transfer clock
Horizontal register transfer clock
Description
Signal output
Supply voltage
Reset gate clock
Horizontal register transfer clock
Horizontal register transfer clock
GND
∗
1
DC bias is generated within the CCD, so that this pin should be grounded externally through a
capacitance of 0.1µF.
–2–
ICX282AQF
Clock Equivalent Circuit Constant
Item
Capacitance between vertical transfer clock
and GND
Symbol
Cφ
V1
γ,
Cφ
V3
γ
Cφ
V1B
, Cφ
V3B
Cφ
V2
, Cφ
V4
Cφ
V1
γ
2
, Cφ
V3
γ
4
Cφ
V1B2
, Cφ
V3B4
Cφ
V23
γ,
Cφ
V41
γ
Cφ
V23B
, Cφ
V41B
Capacitance between vertical transfer clocks
Cφ
V1
γ
3
γ
Cφ
V1B3B
Cφ
V1
γ
3B
, Cφ
V1B3
γ
Cφ
V24
Cφ
V1
γ
1B
, Cφ
V3
γ
3B
Capacitance between horizontal transfer clock
and GND
Capacitance between horizontal transfer clocks
Capacitance between reset gate clock and GND
Capacitance between substrate clock and GND
Vertical transfer clock series resistor
Vertical transfer clock ground resistor
Horizontal transfer clock series resistor
Cφ
H1
Cφ
H2
Cφ
HH
Cφ
RG
Cφ
SUB
R
1
γ,
R
3
γ
R
1B
, R
2
, R
3B
, R
4
R
GND
Rφ
H
Min.
Typ.
1800
6800
5600
560
680
180
270
56
330
91
120
100
82
62
110
5
1500
62
43
16
7.5
Max. Unit Remarks
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
Ω
Ω
Ω
Ω
Note 1)
γ
= A, C for each vertical transfer clock capacitance.
Note 2)
The relationships of V1A = V1C and V3A = V3C are established for each vertical transfer clock
capacitance.
Note 3)
Cφ
V1A1C
and Cφ
V3A3C
are sufficiently small relative to other capacitance between vertical transfer
clocks, and are also below the measurement limit, so these are omitted from the equivalent circuit
diagrams and the above table.
Vφ
2
R
2
Cφ
V1
γ
3
γ
Cφ
V23
γ
Vφ
3
γ
(
γ
= A, C)
R
3
γ
Vφ
1
γ
(
γ
= A, C)
R
1
γ
Cφ
V24
Cφ
V1
γ
2
Rφ
H
Hφ
1A
Rφ
H
Hφ
2A
Cφ
V1B2
Cφ
V1
γ
Cφ
V1
γ
1B
Cφ
V1B3
γ
Cφ
V1B
Cφ
V4
Cφ
V41
γ
Vφ
1B
R
1B
Cφ
V41B
R
GND
R
4
Vφ
4
Cφ
V3B4
Cφ
V1B3B
Cφ
V23B
Cφ
V2
Cφ
V3
γ
Cφ
V3
γ
3B
Cφ
V3B
Cφ
V1
γ
3B
Cφ
V3
γ
4
Rφ
H
Hφ
1B
Cφ
HH
Cφ
H1
Cφ
H2
Rφ
H
Hφ
2B
R
3B
Vφ
3B
Vertical transfer clock equivalent circuit
–5–
Horizontal transfer clock equivalent circuit
stm32/stm8
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EEWORLD
