V62C1162096LL-120MI datasheet, PDF

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V62C1162096LL-120MI: DescriptionStandard SRAM, 128KX16, 120ns, CMOS, PBGA48, 6 X 8 MM, MICRO, BGA-48; Categorystorage storage; File Size112KB，11 Pages; ManufacturerMosel Vitelic Corporation ( MVC ); Websitehttp://www.moselvitelic.com

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V62C1162096LL-120MI Overview

Standard SRAM, 128KX16, 120ns, CMOS, PBGA48, 6 X 8 MM, MICRO, BGA-48

V62C1162096LL-120MI Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Mosel Vitelic Corporation ( MVC )
Parts packaging code	BGA
package instruction	TFBGA, BGA48,6X8,30
Contacts	48
Reach Compliance Code	unknown
ECCN code	3A991.B.2.A
Maximum access time	120 ns
I/O type	COMMON
JESD-30 code	R-PBGA-B48
JESD-609 code	e0
length	8 mm
memory density	2097152 bit
Memory IC Type	STANDARD SRAM
memory width	16
Number of functions	1
Number of terminals	48
word count	131072 words
character code	128000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	128KX16
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Encapsulate equivalent code	BGA48,6X8,30
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	2 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum standby current	0.000001 A
Minimum standby current	1 V
Maximum slew rate	0.03 mA
Maximum supply voltage (Vsup)	2.2 V
Minimum supply voltage (Vsup)	1.8 V
Nominal supply voltage (Vsup)	2 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	0.75 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	6 mm
Base Number Matches	1

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V62C1162096L(L)

Ultra Low Power

128K x 16 CMOS SRAM

Features

• Ultra Low-power consumption

- Active: 35mA I

at 70ns

- Stand-by: 10

A (CMOS input/output)

A (CMOS input/output, L version)

• 70/85/100/120 ns access time

• Equal access and cycle time

• Single +1.8V to 2.2V Power Supply

• Tri-state output

• Automatic power-down when deselected

• Multiple center power and ground pins for

improved noise immunity

• Individual byte controls for both Read and

Write cycles

• Available in 44 pin TSOPII / 48-fpBGA / 48-

BGA

Functional Description

The V62C1162096L is a Low Power CMOS Static

RAM organized as 131,072 words by 16 bits. Easy

Memory expansion is provided by an active LOW (CE)

and (OE) pin.

This device has an automatic power-down mode feature

when deselected. Separate Byte Enable controls (BLE

and BHE) allow individual bytes to be accessed. BLE

controls the lower bits I/O1 - I/O8. BHE controls the

upper bits I/O9 - I/O16.

Writing to these devices is performed by taking Chip

Enable (CE) with Write Enable (WE) and Byte Enable

(BLE/BHE) LOW.

Reading from the device is performed by taking Chip

Enable (CE) with Output Enable (OE) and Byte Enable

(BLE/BHE) LOW while Write Enable (WE) is held

HIGH.

Logic Block Diagram

Pre-Charge Circuit

TSOPII / 48-fpBGA / 48-µBGA

(See nest page)

I/O1

I/O2

I/O3

I/O4

Vcc

Vss

I/O5

I/O6

I/O7

I/O8

A16

A15

A14

A13

A12

BHE

BLE

I/O16

I/O15

I/O14

I/O13

Vss

Vcc

I/O12

I/O11

I/O10

I/O9

A10

A11

Row Select

Vcc

Vss

Memory Array

1024 X 2048

I/O1 - I/O8

I/O9 - I/O16

Data

Cont

Data

Cont

I/O Circuit

Column Select

A10 A11 A12 A13 A14 A15 A16

BHE

BLE

REV. 1.1

April

2001 V62C1162096L(L)

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