CMOS Static RAM
for Automotive Applications
256K (32K x 8-Bit)
Features
◆
◆
◆
IDT71256SA
Description
The IDT71256SA is a 262,144-bit high-speed Static RAM organized
as 32K x 8. It is fabricated using IDT’s high-perfomance, high-reliability
CMOS technology. This state-of-the-art technology, combined with
innovative circuit design techniques, provides a cost-effective solution for
high-speed memory needs for automotive applications.
The IDT71256SA has an output enable pin which operates as fast as
6ns, with address access times as fast as 12ns. All bidirectional inputs and
outputs of the IDT71256SA are TTL-compatible and operation is from a
single 5V supply. Fully static asynchronous circuitry is used, requiring no
clocks or refresh for operation.
The IDT71256SA is packaged in 28-pin, 300 mil (SOIC).
◆
◆
◆
◆
32K x 8 advanced high-speed CMOS static RAM
Automotive temperature options
Equal access and cycle times
– Automotive: 12/15/20/25/35/55ns
One Chip Select plus one Output Enable pin
Bidirectional data inputs and outputs directly
TTL-compatible
Low power consumption via chip deselect
Automotive product available in 28-pin, 300 mil (SOIC)
package
Functional Block Diagram
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
ADDRESS
DECODER
262,144-BIT
MEMORY
ARRAY
,
I/O
0 -
I/O
7
8
8
I/O CONTROL
6819 drw 01
CS
WE
OE
CONTROL
LOGIC
FEBRUARY 2006
1
©2006 Integrated Device Technology, Inc.
DSC-6819/0B
IDT71256SA for Automotive Applications
CMOS Static RAM 256K (32K x 8-Bit)
Automotive Temperature Ranges
Pin Configurations
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Truth Table
(1,2)
CS
OE
L
X
H
X
X
WE
H
L
H
X
X
I/O
DATA
OUT
DATA
IN
High-Z
High-Z
High-Z
Function
Read Data
Write Data
Outputs Disabled
Deselected - Standby (I
SB
)
Deselected - Standby (I
SB1
)
6819 tbl 03
SO28-5
P28-2
P28-1
V
CC
WE
A
13
A
8
A
9
A
11
OE
A
10
CS
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
6819 drw 02
L
L
L
H
V
HC
(3)
NOTES:
1. H = V
IH
, L = V
IL
, x = Don't care.
2. V
LC
= 0.2V, V
HC
= V
CC
–0.2V.
V
3. Other inputs
≥V
HC
or
≤
LC
.
,
DIP/SOJ
Top View
OE
A
11
A
9
A
8
A
13
WE
V
CC
A
14
A
12
A
7
A
6
A
5
A
4
A
3
22
23
24
25
26
27
28
1
2
3
4
5
6
7
Recommended Operating
Temperature and Supply Voltage
Grade
Automotive Grade 1
21
20
19
18
17
16
15
14
13
12
11
10
9
8
Temperature
-40°C to +125°C
-40°C to +105°C
-40°C to +85°C
0°C to +70°C
V
SS
0V
0V
0V
0V
V
DD
See Below
See Below
See Below
See Below
6819 tbl 01
SO28-8
A
10
CS
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
0
A
1
A
2
Automotive Grade 2
Automotive Grade 3
Automotive Grade 4
,
Recommended DC Operating
Conditions
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
-0.5
(1)
Typ.
5.0
0
____
Max.
5.5
0
V
CC
+0.5
0.8
(1)
Unit
V
V
V
V
6819 tbl 04
TSOP
Top View
Absolute Maximum Ratings
Symbol
V
CC
V
TERM
T
BIAS
T
J
T
STG
P
T
I
OUT
Rating
Supply Voltage
Relative to GND
Terminal Voltage
Relative to GND
Temperature Under Bias
Junction Temperature Range
Storage Temperature
Power Dissipation
DC Output Current
6819 drw 02a
____
(1)
Value
-0.5 to +7.0
-0.5 to V
CC
+0.5
-55 to +125
-40 to +150
-65 to +150
1.0
50
Unit
V
V
o
NOTE:
1. Refer to maximum overshoot/undershoot diagram below. The measured
voltage at device pin should not exceed half sinusoidal wave with 2V peak and
half period of 2ns.
Maximum Overshoot/Undershoot
V
IH
+2V
2ns
V
IL
2ns
-2V
6819 drw 10
C
C
C
o
o
W
mA
6819 tbl 02
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2
IDT71256SA for Automotive Applications
CMOS Static RAM 256K (32K x 8-Bit)
Automotive Temperature Ranges
DC Electrical Characteristics
(V
CC
= 5.0V ± 10%, Automotive Temperature Ranges)
IDT71256SA
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Conditions
V
CC
= Max., V
IN =
GND to V
CC
V
CC
= Max.,
CS
= V
IH
, V
OUT
= GND to V
CC
I
OL
= 8mA, V
CC
= Min.
I
OH
= -4mA, V
CC
= Min.
Min.
___
___
Max.
5
5
0.4
___
Unit
µA
µA
V
V
6819 tbl 05
___
2.4
DC Electrical Characteristics
(1)
Symbol
Icc
I
SB
Parameter
Dynamic Operating Current
CS
< V
IL
, Outputs Open, V
CC
= Max., f = f
MAX
(2)
Standby Power Supply Current (TTL Level)
CS
> V
IH
, Outputs Open, V
CC
= Max., f = f
MAX
(2)
Standby Power Supply Current (CMOS Level)
CS
> V
HC
, Outputs Open, V
CC
= Max., f = 0
(2)
,
V
IN
< V
LC
or V
IN
> V
HC
(V
CC
= 5.0V ± 10%, V
LC
= 0.2V, V
HC
= V
CC
–0.2V, Automotive Temperature Ranges)
71256SA12
90
50
71256SA15
80
30
71256SA20
70
20
71256SA25
70
20
71256SA35
70
20
71256SA55
70
20
Unit
mA
mA
I
SB1
15
15
15
15
15
15
mA
6819 tbl 10
NOTES:
1. All values are maximum guaranteed values.
2. f
MAX
= 1/t
RC
(all address inputs are cycling at f
MAX
); f = 0 means no address input lines are changing.
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
3ns
1.5V
1.5V
See Figures 1 and 2
6819 tbl 07
(T
A
= +25°C, f = 1.0MHz, SOJ package)
Symbol
C
IN
C
I/O
Parameter
(1)
Input Capacitance
I/O Capacitance
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max.
7
7
Unit
pF
pF
6819 tbl 08
Capacitance
NOTE:
1. This parameter is guaranteed by device characterization, but not production
tested.
5V
480Ω
DATA
OUT
30pF*
255Ω
6819 drw 03
5V
480Ω
DATA
OUT
5pF*
255Ω
,
.
6819 drw 04
Figure 1. AC Test Load
*Including jig and scope capacitance.
Figure 2. AC Test Load
(for t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
OW,
and t
WHZ
)
6.42
3
IDT71256SA for Automotive Applications
CMOS Static RAM 256K (32K x 8-Bit)
Automotive Temperature Ranges
AC Electrical Characteristics
71256SA12
Symbol
Parameter
Min.
Max.
(V
CC
= 5.0V ± 10%, Automotive Temperature Ranges)
71256SA15
Min.
Max.
71256SA20
Min.
Max.
71256SA25
Min.
Max.
71256SA35
Min.
Max.
71256SA55
Min.
Max.
Unit
Read Cycle
t
RC
t
AA
t
ACS
t
CLZ
(1)
t
CHZ
(1)
t
OE
t
OLZ
(1)
t
OHZ
(1)
t
OH
t
PU
(1)
t
PD
(1)
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select to Output in Low-Z
Chip Select to Output in High-Z
Output Enable to Output Valid
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
Output Hold from Address Change
Chip Select to Power Up Time
Chip Deselect to Power Down Time
12
____
____
15
____
____
20
____
____
25
____
____
35
____
____
55
____
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12
12
____
15
15
____
20
20
____
25
25
____
35
35
____
55
55
____
____
____
____
____
____
____
4
0
____
4
0
____
4
0
____
4
0
____
4
0
____
4
0
____
6
6
____
7
7
____
10
10
____
11
11
____
12
12
____
15
25
____
0
0
3
0
____
0
0
3
0
____
0
0
3
0
____
0
0
3
0
____
0
0
3
0
____
0
0
3
0
____
6
____
6
____
8
____
10
____
12
____
15
____
____
____
____
____
____
____
12
15
20
25
35
55
Write Cycle
t
WC
t
AW
t
CW
t
AS
t
WP
t
WR
t
DW
t
DH
t
OW
(1)
t
WHZ
(1)
Write Cycle Time
Address Valid to End-of-Write
Chip Select to End-of-Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data Valid to End-of-Write
Data Hold Time
Output Active from End-of-Write
Write Enable to Output in High-Z
12
9
9
0
8
0
6
0
4
0
____
15
10
10
0
10
0
7
0
4
0
____
20
15
15
0
15
0
11
0
4
0
____
25
20
20
0
20
0
13
0
4
0
____
35
25
25
0
20
0
13
0
4
0
____
55
40
40
0
35
0
25
0
4
0
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6819 tbl 09
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
6
6
10
11
12
15
NOTE:
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
4
IDT71256SA for Automotive Applications
CMOS Static RAM 256K (32K x 8-Bit)
Automotive Temperature Ranges
Timing Waveform of Read Cycle No. 1
(1)
t
RC
ADDRESS
t
AA
OE
t
OE
CS
t
OLZ
(5)
t
ACS
t
CLZ
DATA
OUT
I
CC
I
SB
(5)
(3)
t
OHZ
t
CHZ
(5)
(5)
HIGH IMPEDANCE
t
PU
DATA
OUT
VALID
t
PD
V
CC
SUPPLY
CURRENT
6819 drw 05
,
Timing Waveform of Read Cycle No. 2
(1,2,4)
t
RC
ADDRESS
t
AA
t
OH
DATA
OUT
PREVIOUS DATA
OUT
VALID
t
OH
DATA
OUT
VALID
6819drw 06
,
NOTES:
1.
WE
is HIGH for Read Cycle.
2. Device is continuously selected,
CS
is LOW.
3. Address must be valid prior to or coincident with the later of
CS
transition LOW; otherwise t
AA
is the limiting parameter.
4.
OE
is LOW.
5. Transition is measured ±200mV from steady state.
6.42
5
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