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FDC6321CD84Z

Description
Small Signal Field-Effect Transistor, 0.00068A I(D), 25V, 2-Element, N-Channel and P-Channel, Silicon, Metal-oxide Semiconductor FET, SUPERSOT-6
CategoryDiscrete semiconductor    The transistor   
File Size306KB,11 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
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FDC6321CD84Z Overview

Small Signal Field-Effect Transistor, 0.00068A I(D), 25V, 2-Element, N-Channel and P-Channel, Silicon, Metal-oxide Semiconductor FET, SUPERSOT-6

FDC6321CD84Z Parametric

Parameter NameAttribute value
MakerFairchild
Parts packaging codeSOT
package instructionSMALL OUTLINE, R-PDSO-G6
Contacts6
Reach Compliance Codeunknown
ECCN codeEAR99
ConfigurationSEPARATE, 2 ELEMENTS
Minimum drain-source breakdown voltage25 V
Maximum drain current (ID)0.00068 A
Maximum drain-source on-resistance0.45 Ω
FET technologyMETAL-OXIDE SEMICONDUCTOR
JESD-30 codeR-PDSO-G6
Number of components2
Number of terminals6
Operating modeENHANCEMENT MODE
Maximum operating temperature150 °C
Package body materialPLASTIC/EPOXY
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Polarity/channel typeN-CHANNEL AND P-CHANNEL
Certification statusNot Qualified
surface mountYES
Terminal formGULL WING
Terminal locationDUAL
transistor applicationsSWITCHING
Transistor component materialsSILICON
Base Number Matches1
April 1999
FDC6321C
Dual N & P Channel , Digital FET
General Description
These dual N & P Channel logic level enhancement mode
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance. This device has been designed
especially for low voltage applications as a replacement for
digital transistors in load switching applications. Since bias
resistors are not required this dual digital FET can replace
several digital transistors with different bias resistors.
Features
N-Ch 25 V, 0.68 A, R
DS(ON)
= 0.45
@ V
GS
= 4.5 V
P-Ch -25 V, -0.46 A, R
DS(ON)
= 1.1
@ V
GS
= -4.5 V.
Very low level gate drive requirements allowing direct
operation in 3 V circuits. V
GS(th)
< 1.0V.
Gate-Source Zener for ESD ruggedness.
>6kV Human Body Model
Replace multiple dual NPN & PNP digital transistors.
SOT-23
SuperSOT
TM
-6
Mark:.321
SuperSOT
TM
-8
SO-8
SOT-223
SOIC-16
D2
S1
D1
4
3
G2
5
2
SuperSOT
TM
-6
S2
G1
6
1
Absolute Maximum Ratings
Symbol
Parameter
T
A
= 25
o
C unless other wise noted
N-Channel
P-Channel
Units
V
DSS
, V
CC
V
GSS
, V
IN
I
D
, I
O
P
D
T
J
,T
STG
ESD
Drain-Source Voltage, Power Supply Voltage
Gate-Source Voltage,
Drain/Output Current
- Continuous
- Pulsed
Maximum Power Dissipation
(Note 1a)
(Note 1b)
25
8
0.68
2
0.9
0.7
-55 to 150
6
-25
-8
-0.46
-1.5
V
V
A
W
Operating and Storage Tempature Ranger
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm)
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
°C
kV
THERMAL CHARACTERISTICS
R
θJA
R
θJC
(Note 1a)
(Note 1)
140
60
°C/W
°C/W
© 1999 Fairchild Semiconductor Corporation
FDC6321C.RevB

FDC6321CD84Z Related Products

FDC6321CD84Z FDC6321CL99Z FDC6321CS62Z
Description Small Signal Field-Effect Transistor, 0.00068A I(D), 25V, 2-Element, N-Channel and P-Channel, Silicon, Metal-oxide Semiconductor FET, SUPERSOT-6 Small Signal Field-Effect Transistor, 0.00068A I(D), 25V, 2-Element, N-Channel and P-Channel, Silicon, Metal-oxide Semiconductor FET, SUPERSOT-6 Small Signal Field-Effect Transistor, 0.00068A I(D), 25V, 2-Element, N-Channel and P-Channel, Silicon, Metal-oxide Semiconductor FET, SUPERSOT-6
Maker Fairchild Fairchild Fairchild
Parts packaging code SOT SOT SOT
package instruction SMALL OUTLINE, R-PDSO-G6 SMALL OUTLINE, R-PDSO-G6 SMALL OUTLINE, R-PDSO-G6
Contacts 6 6 6
Reach Compliance Code unknown unknown unknown
ECCN code EAR99 EAR99 EAR99
Configuration SEPARATE, 2 ELEMENTS SEPARATE, 2 ELEMENTS SEPARATE, 2 ELEMENTS
Minimum drain-source breakdown voltage 25 V 25 V 25 V
Maximum drain current (ID) 0.00068 A 0.00068 A 0.00068 A
Maximum drain-source on-resistance 0.45 Ω 0.45 Ω 0.45 Ω
FET technology METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR
JESD-30 code R-PDSO-G6 R-PDSO-G6 R-PDSO-G6
Number of components 2 2 2
Number of terminals 6 6 6
Operating mode ENHANCEMENT MODE ENHANCEMENT MODE ENHANCEMENT MODE
Maximum operating temperature 150 °C 150 °C 150 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
Package shape RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE
Polarity/channel type N-CHANNEL AND P-CHANNEL N-CHANNEL AND P-CHANNEL N-CHANNEL AND P-CHANNEL
Certification status Not Qualified Not Qualified Not Qualified
surface mount YES YES YES
Terminal form GULL WING GULL WING GULL WING
Terminal location DUAL DUAL DUAL
transistor applications SWITCHING SWITCHING SWITCHING
Transistor component materials SILICON SILICON SILICON
Base Number Matches 1 1 1

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